Gopalakrishnan Vijayan

Publication Activity (10 Years)

Years Active: 1982-1997
Publications (10 Years): 0

Publications

Sergey Gavrilov, Alexey Glebov, S. Rusakov, David T. Blaauw, Larry G. Jones, Gopalakrishnan Vijayan
Fast power loss calculation for digital static CMOS circuits. ED&TC (1997)
Sergey Gavrilov, Alexey Glebov, Satyamurthy Pullela, S. C. Moore, Abhijit Dharchoudhury, Rajendran Panda, Gopalakrishnan Vijayan, David T. Blaauw
Library-less synthesis for static CMOS combinational logic circuits. ICCAD (1997)
Vinod Narayananan, David LaPotin, Rajesh Gupta, Gopalakrishnan Vijayan
PEPPER - a timing driven early floorplanner. ICCD (1995)
Vijay S. Iyengar, Gopalakrishnan Vijayan
Optimized test application timing for AC test. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11 (11) (1992)
Pradip Bose, David LaPotin, Gopalakrishnan Vijayan, Sungho Kim
Workload-Driven Floorplanning for MIPS Optimization. ICCD (1992)
Vijay S. Iyengar, Gopalakrishnan Vijayan
Test Application Timing: The Unexplored Issue in AC Test. ITC (1991)
Gopalakrishnan Vijayan
Generalization of Min-Cut Partitioning to Tree Structures and Its Applications. IEEE Trans. Computers 40 (3) (1991)
Ananth V. Iyer, H. Donald Ratliff, Gopalakrishnan Vijayan
On an edge ranking problem of trees and graphs. Discret. Appl. Math. 30 (1) (1991)
Gopalakrishnan Vijayan, Ren-Song Tsay
A new method for floor planning using topological constraint reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10 (12) (1991)
Jan-Ming Ho, Gopalakrishnan Vijayan, C. K. Wong
Planar topological routing of pad nets. Integr. 11 (3) (1991)
Gopalakrishnan Vijayan, Ren-Song Tsay
Floorplanning by Topological Constraint Reduction. ICCAD (1990)
Jan-Ming Ho, Majid Sarrafzadeh, Gopalakrishnan Vijayan, Chak-Kuen Wong
Pad minimization for planar routing of multiple power nets. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9 (4) (1990)
Gopalakrishnan Vijayan
Partitioning logic on graph structures to minimize routing cost. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9 (12) (1990)
Jan-Ming Ho, Majid Sarrafzadeh, Gopalakrishnan Vijayan, Chak-Kuen Wong
Layer assignment for multichip modules. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9 (12) (1990)
Jan-Ming Ho, Gopalakrishnan Vijayan, Chak-Kuen Wong
New algorithms for the rectilinear Steiner tree problem. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9 (2) (1990)
Gopalakrishnan Vijayan, H. H. Chen, Chak-Kuen Wong
On VHV-routing in channels with irregular boundaries. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8 (2) (1989)
Gopalakrishnan Vijayan
Min-cost Partitioning on a Tree Structure and Applications. DAC (1989)
Jan-Ming Ho, Gopalakrishnan Vijayan, Chak-Kuen Wong
Constructing the optimal rectilinear Steiner tree derivable from a minimum spanning tree. ICCAD (1989)
Jan-Ming Ho, Gopalakrishnan Vijayan, C. K. Wong
A New Approach to the Rectilinear Steiner Tree Problem. DAC (1989)
Ananth V. Iyer, H. Donald Ratliff, Gopalakrishnan Vijayan
Optimal Node Ranking of Trees. Inf. Process. Lett. 28 (5) (1988)
Jeremy P. Spinrad, Gopalakrishnan Vijayan, Douglas B. West
An improved edge bound on the interval number of a graph. J. Graph Theory 11 (3) (1987)
Jeremy P. Spinrad, Gopalakrishnan Vijayan
Worst case analysis of a graph coloring algorithm. Discret. Appl. Math. 12 (1) (1985)
Gopalakrishnan Vijayan, Avi Wigderson
Rectilinear Graphs and their Embeddings. SIAM J. Comput. 14 (2) (1985)
Richard J. Lipton, Jacobo Valdes, Gopalakrishnan Vijayan, Stephen C. North, Robert Sedgewick
VLSI Layout as Programming. ACM Trans. Program. Lang. Syst. 5 (3) (1983)
Richard J. Lipton, Stephen C. North, Robert Sedgewick, Jacobo Valdes, Gopalakrishnan Vijayan
ALI: A procedural language to describe VLSI layouts. DAC (1982)