Ren-Song Tsay

Publication Activity (10 Years)

Years Active: 1988-2024
Publications (10 Years): 29

Top Topics

Compact Representations

Generation Algorithm

Top Venues

Publications

You-En Wu, Hsin-I Wu, Kuo-Cheng Chin, Yi-Chun Yang, Ren-Song Tsay
Accelerate Large Language Model Inference on Edge TPU with OpenVX framework. AICAS (2024)
Hsuan-Yi Lin, Ren-Song Tsay
Beyond Time-Quantum: A Basic-Block FDA Approach for Accurate System Computing Performance Estimation. ASPDAC (2024)
Yi-Chun Yang, Ren-Song Tsay
A Decentralized Solution for Secure Management of IoT Access Rights. ICR (2023)
Wei-Hsin Chang, Ren-Song Tsay
A Secure and Reliable Private Key Recovery Method. ICCE-Taiwan (2023)
Yi-Chun Yang, Ren-Song Tsay
Ureka: A Decentralized and Secure System for Managing Personal IoT Devices. ICCE-Taiwan (2023)
Wei-Hsin Chang, Ren-Song Tsay
An Owner-managed Indirect-Permission Social Authentication Method for Private Key Recovery. CoRR (2022)
Hsu-Hsun Chin, Ren-Song Tsay, Hsin-I Wu
An Adaptive High-Performance Quantization Approach for Resource-Constrained CNN Inference. AICAS (2022)
Chong-Yin Lu, Ren-Song Tsay, Weyshin Chang
An Embedded CNN Design for Edge Devices Based on Logarithmic Computing. VLSI-DAT (2022)
Hsin-Yu Ho, Ren-Song Tsay
An Effective Early Multi-core System Shared Cache Design Method Based on Reuse-distance Analysis. CoRR (2021)
Li-Chun Chen, Hsin-I Wu, Ren-Song Tsay
Automatic Timing-Coherent Transactor Generation for Mixed-level Simulations. CoRR (2021)
Zheng-Xun Jiang, Ren-Song Tsay
A Double-Linked Blockchain Approach Based on Proof-of-Refundable-Tax Consensus Algorithm. CoRR (2021)
Hsu-Hsun Chin, Ren-Song Tsay, Hsin-I Wu
A High-Performance Adaptive Quantization Approach for Edge CNN Applications. CoRR (2021)
Cheng-Lin Tsai, Ren-Song Tsay
A Fast-and-Effective Early-Stage Multi-level Cache Optimization Method Based on Reuse-Distance Analysis. CoRR (2021)
Wei-Yi Kuo, Ren-Song Tsay
3LSAA: A Secure And Privacy-preserving Zero-knowledge-based Data-sharing Approach Under An Untrusted Environment. CoRR (2021)
Chien-Hao Chen, Ren-Song Tsay
Analytical Process Scheduling Optimization for Heterogeneous Multi-core Systems. CoRR (2021)
Hsuan-Yi Lin, Ren-Song Tsay
A Precise Program Phase Identification Method Based on Frequency Domain Analysis. CoRR (2021)
Yun Chang, Hsin-I Wu, Ren-Song Tsay
An Effective Parallel Program Debugging Approach Based on Timing Annotation. CoRR (2021)
Hsin-I Wu, Ren-Song Tsay, Hsu-Hsun Chin
VIRA: a virtualization assisted deterministic system-level simulations. SAC (2020)
Hsin-I Wu, Da-Yi Guo, Hsu-Hsun Chin, Ren-Song Tsay
A Pipeline-Based Scheduler for Optimizing Latency of Convolution Neural Network Inference over Heterogeneous Multicore Systems. AICAS (2020)
Tsung-Ying Lu, Hsu-Hsun Chin, Hsin-I Wu, Ren-Song Tsay
A Very Compact Embedded CNN Processor Design Based on Logarithmic Computing. CoRR (2020)
Yin-Chun Ling, Hsu-Hsun Chin, Hsin-I Wu, Ren-Song Tsay
Designing A Compact Convolutional Neural Network Processor on Embedded FPGAs. GCAIoT (2020)
Hsin-I Wu, Da-Yi Guo, Ren-Song Tsay
A Virtualization-Assisted Full-System Simulation Approach for the Verification of System Intercomponent Interactions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (12) (2020)
Asheen Lateilla Richards, Ren-Song Tsay
An Optimal Slack-Based Course Scheduling Algorithm for Personalised Study Plans. ICEIT (2020)
Kuo-Cheng Chin, Ren-Song Tsay, Hsin-I Wu
A Heuristic Region-based Concurrency Bug Testing Approach. ISPA/BDCloud/SocialCom/SustainCom (2020)
Hsin-I Wu, Ren-Song Tsay, Fong-Yuan Chang
CORONA: A k-COnnected RObust Interconnection Network Generation Algorithm. VLSI-DAT (2020)
Hsin-I Wu, Chi-Kang Chen, Tsung-Ying Lu, Ren-Song Tsay
A highly efficient full-system virtual prototype based on virtualization-assisted approach. DATE (2018)
Chi-Kang Chen, Hsin-I Wu, Chi-Ting Hsiao, Ren-Song Tsay
An accurate and flexible early memory system power evaluation approach using a microcomponent method. CODES+ISSS (2016)
Hsuan-Man Chen, Chi-Kang Chen, Hsin-I Wu, Ren-Song Tsay
An Accurate Crowdsourcing-Based Adaptive Fall Detection Approach Using Smart Devices. ICHI (2016)
Hsuan-Man Chen, Chi-Kang Chen, Hsin-I Wu, Ren-Song Tsay
Poster Paper: An Accurate Crowdsourcing-Based Adaptive Fall Detection Approach Using Smart Devices. ICHI (2016)
Jyun-Hao Chang, Hsin-I Wu, Hsien-Lun Pai, Ren-Song Tsay, Wai-Kei Mak
Highly Efficient and Effective Approach for Synchronization-Function-Level Parallel Multicore Instruction-Set Simulations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34 (11) (2015)
Zih-Ci Huang, Chi-Kang Chen, Ren-Song Tsay
AROMA: A highly accurate microcomponent-based approach for embedded processor power analysis. ASP-DAC (2015)
Li-Chun Chen, Hsin-I Wu, Ren-Song Tsay
Automatic timing-coherent transactor generation for mixed-level simulations. ASP-DAC (2015)
Shu-Yung Chen, Chien-Hao Chen, Ren-Song Tsay
An activity-sensitive contention delay model for highly efficient deterministic full-system simulations. DATE (2014)
Mao Lin Li, Chen Kang Lo, Li-Chun Chen, Jen-Chieh Yeh, Ren-Song Tsay
A Cycle Count Accurate TLM bus modeling approach. VLSI-DAT (2013)
Meng-Huan Wu, Cheng-Yang Fu, Peng-Chih Wang, Ren-Song Tsay
A distributed timing synchronization technique for parallel multi-core instruction-set simulation. ACM Trans. Embed. Comput. Syst. 12 (1s) (2013)
Chen Kang Lo, Mao Lin Li, Li-Chun Chen, Yi-Shan Lu, Ren-Song Tsay, Hsu-Yao Huang, Jen-Chieh Yeh
Automatic generation of high-speed accurate TLM models for out-of-order pipelined bus. ACM Trans. Embed. Comput. Syst. 13 (1s) (2013)
Chien-Min Lee, Chi-Kang Chen, Ren-Song Tsay
A basic-block power annotation approach for fast and accurate embedded software power estimation. VLSI-SoC (2013)
Fong-Yuan Chang, Ren-Song Tsay, Wai-Kei Mak, Sheng-Hsiung Chen
MANA: A Shortest Path Maze Algorithm Under Separation and Minimum Length NAnometer Rules. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32 (10) (2013)
Fong-Yuan Chang, Ren-Song Tsay, Wai-Kei Mak, Sheng-Hsiung Chen
A separation and minimum wire length constrained maze routing algorithm under nanometer wiring rules. ASP-DAC (2013)
Bo-Han Zeng, Ren-Song Tsay, Ting-Chi Wang
An efficient hybrid synchronization technique for scalable multi-core instruction set simulations. ASP-DAC (2013)
Pei-Chia Patty Lin, Evason Du, Ren-Song Tsay
A fast and accurate instruction-oriented processor simulation approach. VLSI-DAT (2013)
Fan-Wei Yu, Bo-Han Zeng, Yu-Hung Huang, Hsin-I Wu, Che-Rung Lee, Ren-Song Tsay
A critical-section-level timing synchronization approach for deterministic multi-core instruction set simulations. DATE (2013)
Meng-Huan Wu, Peng-Chih Wang, Cheng-Yang Fu, Ren-Song Tsay
An Extended SystemC Framework for Efficient HW/SW Co-Simulation. ACM Trans. Design Autom. Electr. Syst. 17 (2) (2012)
Yu-Hung Huang, Yi-Shan Lu, Hsin-I Wu, Ren-Song Tsay
A non-intrusive timing synchronization interface for hardware-assisted HW/SW co-simulation. DAC (2012)
Chen Kang Lo, Li-Chun Chen, Meng-Huan Wu, Ren-Song Tsay
Cycle-count-accurate processor modeling for fast and accurate system-level simulation. DATE (2011)
Ren-Song Tsay
From academic ideas to practical physical design tools. ISPD (2011)
Meng-Huan Wu, Peng-Chih Wang, Cheng-Yang Fu, Ren-Song Tsay
A high-parallelism distributed scheduling mechanism for multi-core instruction-set simulation. DAC (2011)
Cheng-Yang Fu, Meng-Huan Wu, Ren-Song Tsay
A shared-variable-based synchronization approach to efficient cache coherence simulation for multi-core systems. DATE (2011)
Fong-Yuan Chang, Sheng-Hsiung Chen, Ren-Song Tsay, Wai-Kei Mak
Cut-demand based routing resource allocation and consolidation for routability enhancement. ASP-DAC (2011)
Ching-Te Chiu, Tsun-Hsien Wang, Wei-Ming Ke, Chen-Yu Chuang, Jhih-Siao Huang, Wei-Su Wong, Ren-Song Tsay, Cyuan-Jhe Wu
Real-Time Tone-Mapping Processor with Integrated Photographic and Gradient Compression using 0.13 μm Technology on an Arm Soc Platform. J. Signal Process. Syst. 64 (1) (2011)
Peng-Chih Wang, Meng-Huan Wu, Ren-Song Tsay
DOM: A Data-dependency-Oriented Modeling approach for efficient simulation of OS preemptive scheduling. DATE (2011)
Kai-Li Lin, Chen Kang Lo, Ren-Song Tsay
Source-level timing annotation for fast and accurate TLM computation model generation. ASP-DAC (2010)
Meng-Huan Wu, Wen-Chuan Lee, Chen-Yu Chuang, Ren-Song Tsay
Automatic generation of software TLM in multiple abstraction layers for efficient HW/SW co-simulation. DATE (2010)
Chen Kang Lo, Ren-Song Tsay
Automatic generation of Cycle Accurate and Cycle Count Accurate transaction level bus models from a formal model. ASP-DAC (2009)
Fong-Yuan Chang, Ren-Song Tsay, Wai-Kei Mak
How to consider shorts and guarantee yield rate improvement for redundant wire insertion. ICCAD (2009)
Meng-Huan Wu, Cheng-Yang Fu, Peng-Chih Wang, Ren-Song Tsay
An effective synchronization approach for fast and accurate multi-core instruction-set simulation. EMSOFT (2009)
Yi-Len Lo, Mao Lin Li, Ren-Song Tsay
Cycle count accurate memory modeling in system level design. CODES+ISSS (2009)
Ching-Te Chiu, Tsun-Hsien Wang, Wei-Ming Ke, Chen-Yu Chuang, Jhih-Siao Huang, Wei-Su Wong, Ren-Song Tsay
A 100MHz real-time tone mapping processor with integrated photographic and gradient compression in 0.13 mum technology. SiPS (2008)
Ching-Te Chiu, Tsun-Hsien Wang, Wei-Ming Ke, Chen-Yu Chuang, Jhih-Rong Chen, Rong Yang, Ren-Song Tsay
Design optimization of a global/local tone mapping processor on arm SOC platform for real-time high dynamic range video. ICIP (2008)
Ren-Song Tsay
An Entrepreneurship Emulation Platform. MSE (2007)
Ren-Song Tsay
An exact zero-skew clock routing algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12 (2) (1993)
Jan-Ming Ho, Ren-Song Tsay
Clock tree regeneration. Great Lakes Symposium on VLSI (1992)
Minshine Shih, Ernest S. Kuh, Ren-Song Tsay
Performance-Driven System Partitioning on Multi-Chip Modules. DAC (1992)
Ren-Song Tsay
Exact Zero Skew. ICCAD (1991)
Gopalakrishnan Vijayan, Ren-Song Tsay
A new method for floor planning using topological constraint reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10 (12) (1991)
Ren-Song Tsay, Jürgen Koehl
An Analytic Net Weighting Approach for Performance Optimization in Circuit Placement. DAC (1991)
Gopalakrishnan Vijayan, Ren-Song Tsay
Floorplanning by Topological Constraint Reduction. ICCAD (1990)
Tai-Ming Parng, Ren-Song Tsay
A new approach to sea-of-gates global routing. ICCAD (1989)
Ren-Song Tsay, Ernest S. Kuh, Chi-Ping Hsu
PROUD: a sea-of-gates placement algorithm. IEEE Des. Test 5 (6) (1988)
Ren-Song Tsay, Ernest S. Kuh, Chi-Ping Hsu
Proud: A Fast Sea-of-Gates Placement Algorithm. DAC (1988)