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Yi-Shan Lu
ORCID
Publication Activity (10 Years)
Years Active: 2012-2021
Publications (10 Years): 4
Top Topics
Hardware Software Partitioning
Deontic Logic
Asynchronous Circuits
Proof Theory
Top Venues
ACM Trans. Embed. Comput. Syst.
IEEE Des. Test
HPEC
ICCAD
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Publications
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Samira Ataei
,
Wenmian Hua
,
Yihang Yang
,
Rajit Manohar
,
Yi-Shan Lu
,
Jiayuan He
,
Sepideh Maleki
,
Keshav Pingali
An Open-Source EDA Flow for Asynchronous Logic.
IEEE Des. Test
38 (2) (2021)
Wenmian Hua
,
Yi-Shan Lu
,
Keshav Pingali
,
Rajit Manohar
Cyclone: A Static Timing and Power Engine for Asynchronous Circuits.
ASYNC
(2020)
Vinicius N. Possani
,
Yi-Shan Lu
,
Alan Mishchenko
,
Keshav Pingali
,
Renato P. Ribas
,
André Inácio Reis
Unlocking fine-grain parallelism for AIG rewriting.
ICCAD
(2018)
Chad Voegele
,
Yi-Shan Lu
,
Sreepathi Pai
,
Keshav Pingali
Parallel triangle counting and k-truss identification using graph-centric methods.
HPEC
(2017)
Chen Kang Lo
,
Mao Lin Li
,
Li-Chun Chen
,
Yi-Shan Lu
,
Ren-Song Tsay
,
Hsu-Yao Huang
,
Jen-Chieh Yeh
Automatic generation of high-speed accurate TLM models for out-of-order pipelined bus.
ACM Trans. Embed. Comput. Syst.
13 (1s) (2013)
Yu-Hung Huang
,
Yi-Shan Lu
,
Hsin-I Wu
,
Ren-Song Tsay
A non-intrusive timing synchronization interface for hardware-assisted HW/SW co-simulation.
DAC
(2012)