Jen-Chieh Yeh

Publication Activity (10 Years)

Years Active: 2001-2014
Publications (10 Years): 0

Top Topics

Layered Architecture

Distributed Multimedia

Top Venues

ACM Trans. Embed. Comput. Syst.

Publications

Hsien-Ching Hsieh, Yi-Fa Sun, Jen-Chieh Yeh, Po-Han Huang
3-D stacked memory system architecture exploration by esl virtual platform and reconfigurable stacking memory architecture in 3D-DSP SoC system. ICASSP (2014)
Hsiu-Chuan Shih, Pei-Wen Luo, Jen-Chieh Yeh, Shu-Yen Lin, Ding-Ming Kwai, Shih-Lien Lu, Andre Schaefer, Cheng-Wen Wu
DArT: A Component-Based DRAM Area, Power, and Timing Modeling Tool. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33 (9) (2014)
Po-Han Wang, Gen-Hong Liu, Jen-Chieh Yeh, Tse-Min Chen, Hsu-Yao Huang, Chia-Lin Yang, Shih-Lien Liu, James Greensky
Full system simulation framework for integrated CPU/GPU architecture. VLSI-DAT (2014)
Jen-Chieh Yeh, Chi-Hung Lin, Chun-Nan Liu
Multi-core system performance prediction and analysis at the ESL. Int. J. Comput. Sci. Eng. 9 (1/2) (2014)
Mao Lin Li, Chen Kang Lo, Li-Chun Chen, Jen-Chieh Yeh, Ren-Song Tsay
A Cycle Count Accurate TLM bus modeling approach. VLSI-DAT (2013)
Chen Kang Lo, Mao Lin Li, Li-Chun Chen, Yi-Shan Lu, Ren-Song Tsay, Hsu-Yao Huang, Jen-Chieh Yeh
Automatic generation of high-speed accurate TLM models for out-of-order pipelined bus. ACM Trans. Embed. Comput. Syst. 13 (1s) (2013)
Shin-Shiun Chen, Chun-Kai Hsu, Hsiu-Chuan Shih, Jen-Chieh Yeh, Cheng-Wen Wu
Processor and DRAM integration by TSV-based 3-D stacking for power-aware SOCs. ASP-DAC (2013)
Hsien-Ching Hsieh, Shr-Je Lin, Chun-Nan Liu, Jen-Chieh Yeh, Shing-Wu Tung, Ding-Ming Kwai
A case study: 3-D stacked memory system architecture exploration by ESL virtual platform. VLSI-DAT (2013)
Mao-Yin Wang, Jen-Chieh Yeh
Monitoring and timing prediction in early analyzing and checking performance of interconnection networks at ESL. ISQED (2012)
Yi-Fa Sun, Chun-Nan Liu, Tse-Min Chen, Hsien-Ching Hsieh, Jen-Chieh Yeh, Yung-Chang Chang
Improvement of Multimedia Performance Based on 3-D Stacking Memory Architecture and Software Refinement. HPCC-ICESS (2012)
Jen-Chieh Yeh, Kung-Ming Ji, Shing-Wu Tung, Shau-Yin Tseng
Heterogeneous Multi-core SoC Implementation with System-Level Design Methodology. HPCC (2011)
Chi-Hung Lin, Wen-Tsan Hsieh, Hsien-Ching Hsieh, Chun-Nan Liu, Jen-Chieh Yeh
System-level design exploration for 3-D stacked memory architectures. CODES+ISSS (2011)
Chen-Wei Hsu, Jia-Lu Liao, Shan-Chien Fang, Chia-Chien Weng, Shi-Yu Huang, Wen-Tsan Hsieh, Jen-Chieh Yeh
PowerDepot: integrating IP-based power modeling with ESL power analysis for multi-core SoC designs. DAC (2011)
Wen-Tsan Hsieh, Jen-Chieh Yeh, Shih-Che Lin, Hsing-Chuang Liu, Yi-Siou Chen
System power analysis with DVFS on ESL virtual platform. SoCC (2011)
Zhe-Mao Hsu, Jen-Chieh Yeh, I-Yao Chuang
An accurate system architecture refinement methodology with mixed abstraction-level virtual platform. DATE (2010)
Wen-Tsan Hsieh, Jen-Chieh Yeh, Shi-Yu Huang
PAC duo system power estimation at ESL. ASP-DAC (2010)
Jing-Wun Lin, Chen-Chieh Wang, Chin-Yao Chang, Chung-Ho Chen, Kuen-Jong Lee, Yuan-Hua Chu, Jen-Chieh Yeh, Ying-Chuan Hsiao
Full System Simulation and Verification Framework. IAS (2009)
Zhe-Mao Hsu, I-Yao Chuang, Wen-Chien Su, Jen-Chieh Yeh, Jen-Kuei Yang, Shau-Yin Tseng
System Performance Analyses on PAC Duo ESL Virtual Platform. IIH-MSP (2009)
Jen-Chieh Yeh, Chao-Hsun Chen, Cheng-Wen Wu, Shuo-Fen Kuo
A Systematic Approach to Memory Test Time Reduction. IEEE Des. Test Comput. 25 (6) (2008)
Yu-Tsao Hsing, Chun-Chieh Huang, Jen-Chieh Yeh, Cheng-Wen Wu
SDRAM Delay Fault Modeling and Performance Testing. VTS (2007)
Rei-Fu Huang, Jin-Fu Li, Jen-Chieh Yeh, Cheng-Wen Wu
Raisin: Redundancy Analysis Algorithm Simulation. IEEE Des. Test Comput. 24 (4) (2007)
Jen-Chieh Yeh, Kuo-Liang Cheng, Yung-Fa Chou, Cheng-Wen Wu
Flash Memory Testing and Built-In Self-Diagnosis With March-Like Test Algorithms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (6) (2007)
Po-Yuan Chen, Yi-Ting Yeh, Chao-Hsun Chen, Jen-Chieh Yeh, Cheng-Wen Wu, Jeng-Shen Lee, Yu-Chang Lin
An Enhanced EDAC Methodology for Low Power PSRAM. ITC (2006)
Chen-Hsing Wang, Chih-Yen Lo, Min-Sheng Lee, Jen-Chieh Yeh, Chih-Tsun Huang, Cheng-Wen Wu, Shi-Yu Huang
A network security processor design based on an integrated SOC design and test platform. DAC (2006)
Mu-Hsien Hsu, Yu-Tsao Hsing, Jen-Chieh Yeh, Cheng-Wen Wu
Fault-Pattern Oriented Defect Diagnosis for Flash Memory. MTDT (2006)
Yu-Chun Dawn, Jen-Chieh Yeh, Cheng-Wen Wu, Chia-Ching Wang, Yung-Chen Lin, Chao-Hsun Chen
Flash Memory Die Sort by a Sample Classification Method. Asian Test Symposium (2005)
Jen-Chieh Yeh, Shyr-Fen Kuo, Cheng-Wen Wu, Chih-Tsun Huang, Chao-Hsun Chen
A systematic approach to reducing semiconductor memory test time in mass production. MTDT (2005)
Jin-Fu Li, Jen-Chieh Yeh, Rei-Fu Huang, Cheng-Wen Wu
A built-in self-repair design for RAMs with 2-D redundancy. IEEE Trans. Very Large Scale Integr. Syst. 13 (6) (2005)
Jen-Chieh Yeh, Yan-Ting Lai, Yuan-Yuan Shih, Cheng-Wen Wu, Chien-Hung Ho, Yen-Tai Lin
Flash Memory Built-In Self-Diagnosis with Test Mode Control. VTS (2005)
Chih-Tsun Huang, Jen-Chieh Yeh, Yuan-Yuan Shih, Rei-Fu Huang, Cheng-Wen Wu
On Test and Diagnostics of Flash Memories. Asian Test Symposium (2004)
Jin-Fu Li, Jen-Chieh Yeh, Rei-Fu Huang, Cheng-Wen Wu, Peir-Yuan Tsai, Archer Hsu, Eugene Chow
A Built-In Self-Repair Scheme for Semiconductor Memories with 2-D Redundancy. ITC (2003)
Rei-Fu Huang, Jin-Fu Li, Jen-Chieh Yeh, Cheng-Wen Wu
A Simulator for E aluating Redundancy Analysis Algorithms of Repairable Embedded Memories. IOLTW (2002)
Sau-Kwo Chiu, Jen-Chieh Yeh, Chih-Tsun Huang, Cheng-Wen Wu
Diagonal Test and Diagnostic Schemes for Flash Memorie. ITC (2002)
Jen-Chieh Yeh, Chi-Feng Wu, Kuo-Liang Cheng, Yung-Fa Chou, Chih-Tsun Huang, Cheng-Wen Wu
Flash Memory Built-In Self-Test Using March-Like Algorithm. DELTA (2002)
Rei-Fu Huang, Jin-Fu Li, Jen-Chieh Yeh, Cheng-Wen Wu
A Simulator for Evaluating Redundancy Analysis Algorithms of Repairable Embedded Memories. MTDT (2002)
Kuo-Liang Cheng, Jen-Chieh Yeh, Chih-Wea Wang, Chih-Tsun Huang, Cheng-Wen Wu
RAMSES-FT: A Fault Simulator for Flash Memory Testing and Diagnostics. VTS (2002)
Kuo-Liang Cheng, Chia-Ming Hsueh, Jing-Reng Huang, Jen-Chieh Yeh, Chih-Tsun Huang, Cheng-Wen Wu
Automatic Generation of Memory Built-in Self-Test Cores for System-on-Chip. Asian Test Symposium (2001)