Jin-Fu Li

ORCID

Publication Activity (10 Years)

Years Active: 1999-2023
Publications (10 Years): 26

Top Venues

Publications

Jin-Fu Li
Testing of Computing-In Memories: Faults, Test Algorithms, and Design-for-Testability. DFT (2023)
Yu-Guang Chen, Po-Yeh Huang, Jin-Fu Li
An On-Line Aging Detection and Tolerance Framework for Improving Reliability of STT-MRAMs. ASP-DAC (2023)
Chuan-Han Cheng, Shih-Hsu Huang, Jin-Fu Li
Design and Dataflow for Multibit SRAM-Based MAC Operations. ISOCC (2022)
Jin-Fu Li
Testing and Reliability of Computing-In Memories: Solutions and Challenges. ITC-Asia (2022)
Yu-Cheng Yang, Jin-Fu Li
Fault Modeling and Testing of RRAM-based Computing-In Memories. ITC-Asia (2022)
Jin-Fu Li
Design and Test of Computing-In Memories. ISOCC (2022)
Jin-Fu Li, Jing-Jia Liou
Foreword: ATS 2022. ATS (2022)
Ze-Wei Pan, Jin-Fu Li
DFT-Enhanced Test Scheme for Spin-Transfer-Torque (STT) MRAMs. ITC (2022)
Wei Chang, Yu-Guang Chen, Po-Yeh Huang, Jin-Fu Li
An Aging-Aware CMOS SRAM Structure Design for Boolean Logic In-Memory Computing. DFT (2021)
Yung-Yu Tsai, Jin-Fu Li
Evaluating the Impact of Fault-Tolerance Capability of Deep Neural Networks Caused by Faults. SoCC (2021)
Jin-Fu Li, Tsai-Ling Tsai, Chun-Lung Hsu, Chi-Tien Sun
Testing of Configurable 8T SRAMs for In-Memory Computing. ATS (2020)
Tsung-Fu Hsieh, Jin-Fu Li, Jenn-Shiang Lai, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou
Refresh Power Reduction of DRAMs in DNN Systems Using Hybrid Voting and ECC Method. ITC-Asia (2020)
Wei-Hsuan Yang, Jin-Fu Li, Chun-Lung Hsu, Chi-Tien Sun, Shih-Hsu Huang
A Built-in Self-Test Scheme for TSVs of Logic-DRAM Stacked 3D ICs. 3DIC (2019)
Tsai-Ling Tsai, Jin-Fu Li, Chun-Lung Hsu, Chi-Tien Sun
Testing of In-Memory-Computing 8T SRAMs. DFT (2019)
Tsai-Ling Tsai, Jin-Fu Li, Chun-Lung Hsu, Chi-Tien Sun
Testing stuck-open faults of priority address encoder in content addressable memories. ASP-DAC (2019)
Fan-Hsuan Tang, Hsu-Yu Kao, Shih-Hsu Huang, Jin-Fu Li
3D Test Wrapper Chain Optimization with I/O Cells Binding Considered. 3DIC (2019)
Yu-Ting Li, Jin-Fu Li, Chun-Lung Hsu, Chi-Tien Sun
Diagnosis of Resistive Nonvolatile-8T SRAMs. ISOCC (2018)
Jin-Fu Li, Jiun-Lang Huang
Conference Reports: Report on 2017 IEEE Asian Test Symposium. IEEE Des. Test 35 (2) (2018)
Kuan-Te Wu, Jin-Fu Li, Chih-Yen Lo, Jenn-Shiang Lai, Ding-Ming Kwai, Yung-Fa Chou
A channel-sharable built-in self-test scheme for multi-channel DRAMs. ASP-DAC (2018)
Li-Wei Deng, Jin-Fu Li, Yong-Xiao Chen
Modeling and testing comparison faults of memristive ternary content addressable memories. ETS (2018)
Chia-Ming Chang, Yong-Xiao Chen, Jin-Fu Li
A built-in self-test scheme for classifying refresh periods of DRAMs. ETS (2017)
Tsung-Fu Hsieh, Jin-Fu Li, Kuan-Te Wu, Jenn-Shiang Lai, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou
Software-hardware-cooperated built-in self-test scheme for channel-based DRAMs. ITC-Asia (2017)
Tzu-Ying Lin, Yong-Xiao Chen, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou
A Test Method for Finding Boundary Currents of 1T1R Memristor Memories. ATS (2016)
Han-Yu Wu, Yong-Xiao Chen, Jin-Fu Li
A built-in method for measuring the delay of TSVs in 3D ICs. ETS (2016)
Chih-Sheng Hou, Yong-Xiao Chen, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou
A built-in self-repair scheme for DRAMs with spare rows, columns, and bits. ITC (2016)
Yu-Ting Li, Yong-Xiao Chen, Jin-Fu Li
Fault modeling and testing of resistive nonvolatile-8T SRAMs. VTS (2016)
Chih-Sheng Hou, Jin-Fu Li
High Repair-Efficiency BISR Scheme for RAMs by Reusing Bitmap for Bit Redundancy. IEEE Trans. Very Large Scale Integr. Syst. 23 (9) (2015)
Che-Wei Chou, Jin-Fu Li, Yun-Chao Yu, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou
Hierarchical Test Integration Methodology for 3-D ICs. IEEE Des. Test 32 (4) (2015)
Yong-Xiao Chen, Jin-Fu Li
Fault modeling and testing of 1T1R memristor memories. VTS (2015)
Che-Wei Chou, Yong-Xiao Chen, Jin-Fu Li
Testing Inter-Word Coupling Faults of Wide I/O DRAMs. ATS (2015)
Chi-Chun Yang, Jin-Fu Li, Yun-Chao Yu, Kuan-Te Wu, Chih-Yen Lo, Chao-Hsun Chen, Jenn-Shiang Lai, Ding-Ming Kwai, Yung-Fa Chou
A hybrid built-in self-test scheme for DRAMs. VLSI-DAT (2015)
Chih-Sheng Hou, Jin-Fu Li, Ting-Jun Fu
A BIST Scheme With the Ability of Diagnostic Data Compression for RAMs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33 (12) (2014)
Chih-Sheng Hou, Jin-Fu Li
Testing Disturbance Faults in Various NAND Flash Memories. J. Electron. Test. 30 (6) (2014)
Kuan-Te Wu, Jin-Fu Li, Yun-Chao Yu, Chih-Sheng Hou, Chi-Chun Yang, Ding-Ming Kwai, Yung-Fa Chou, Chih-Yen Lo
Intra-channel Reconfigurable Interface for TSV and Micro Bump Fault Tolerance in 3-D RAMs. ATS (2014)
Yu-Jen Huang, Jin-Fu Li
Yield-enhancement schemes for multicore processor and memory stacked 3D ICs. ACM Trans. Embed. Comput. Syst. 13 (3s) (2014)
Yun-Chao You, Chi-Chun Yang, Jin-Fu Li, Chih-Yen Lo, Chao-Hsun Chen, Jenn-Shiang Lai, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu
BIST-Assisted Tuning Scheme for Minimizing IO-Channel Power of TSV-Based 3D DRAMs. ATS (2014)
Iris Hui-Ru Jiang, Natarajan Viswanathan, Tai-Chen Chen, Jin-Fu Li
The overview of 2014 CAD contest at ICCAD. ICCAD (2014)
Yong-Xiao Chen, Jin-Fu Li
Testing of Non-volatile Logic-Based System Chips. ATS (2014)
Chih-Sheng Hou, Jin-Fu Li
Testing Disturbance Faults in Various NAND Flash Memories. Asian Test Symposium (2013)
Yun-Chao You, Chih-Sheng Hou, Li-Jung Chang, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu
A hybrid ECC and redundancy technique for reducing refresh power of DRAMs. VTS (2013)
Chih-Sheng Hou, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu
An FPGA-based test platform for analyzing data retention time distribution of DRAMs. VLSI-DAT (2013)
Jin-Fu Li, Cheng-Wen Wu, Masahiro Aoyagi, Meng-Fan Marvin Chang, Ding-Ming Kwai
Special session 4C: Hot topic 3D-IC design and test. VTS (2013)
Chi-Chun Yang, Che-Wei Chou, Jin-Fu Li
A TSV Repair Scheme Using Enhanced Test Access Architecture for 3-D ICs. Asian Test Symposium (2013)
Chih-Sheng Hou, Jin-Fu Li
Allocation of RAM built-in self-repair circuits for SOC dies of 3D ICs. VTS (2013)
Che-Wei Chou, Yu-Jen Huang, Jin-Fu Li
A Built-In Self-Repair Scheme for 3-D RAMs With Interdie Redundancy. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32 (4) (2013)
Chun-Kai Lai, Yu-Jen Huang, Jin-Fu Li
A Self-Repair Technique for Content Addressable Memories with Address-Input-Free Writing Function. J. Inf. Sci. Eng. 29 (3) (2013)
Li-Jung Chang, Yu-Jen Huang, Jin-Fu Li
Area and reliability efficient ECC scheme for 3D RAMs. VLSI-DAT (2012)
Shun-Hsun Yang, Yu-Jen Huang, Jin-Fu Li
A Low-Power Ternary Content Addressable Memory With Pai-Sigma Matchlines. IEEE Trans. Very Large Scale Integr. Syst. 20 (10) (2012)
Chih-Sheng Hou, Jin-Fu Li
Disturbance fault testing on various NAND flash memories. ETS (2012)
Yong-Xiao Chen, Yu-Jen Huang, Jin-Fu Li
Test cost optimization technique for the pre-bond test of 3D ICs. VTS (2012)
Yu-Jen Huang, Jin-Fu Li
Built-In Self-Repair Scheme for the TSVs in 3-D ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31 (10) (2012)
Yu-Jen Huang, Jin-Fu Li
Low-Cost Self-Test Techniques for Small RAMs in SOCs Using Enhanced IEEE 1500 Test Wrappers. IEEE Trans. Very Large Scale Integr. Syst. 20 (11) (2012)
Yun-Chao You, Che-Wei Chou, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu
A built-in self-test scheme for 3D RAMs. ITC (2012)
Jin-Fu Li
Testing and Diagnosing Comparison Faults of TCAMs with Asymmetric Cells. IEEE Trans. Computers 61 (11) (2012)
Yu-Jen Huang, Jin-Fu Li, Che-Wei Chou
Post-bond test techniques for TSVs with crosstalk faults in 3D ICs. VLSI-DAT (2012)
Ting-Ju Chen, Jin-Fu Li, Tsu-Wei Tseng
Cost-Efficient Built-In Redundancy Analysis With Optimal Repair Rate for RAMs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31 (6) (2012)
Cheng-Wen Wu, Shyue-Kung Lu, Jin-Fu Li
On test and repair of 3D random access memory. ASP-DAC (2012)
Yu-Jen Huang, Jin-Fu Li, Ji-Jan Chen, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu
A built-in self-test scheme for the post-bond test of TSVs in 3D ICs. VTS (2011)
Tsu-Wei Tseng, Jin-Fu Li
A Low-Cost Built-In Redundancy-Analysis Scheme for Word-Oriented RAMs With 2-D Redundancy. IEEE Trans. Very Large Scale Integr. Syst. 19 (11) (2011)
Tsu-Wei Tseng, Jin-Fu Li
SETBIST: An Soft-Error Tolerant Built-In Self-Test Scheme for Random Access Memories. J. Inf. Sci. Eng. 27 (2) (2011)
Chih-Sheng Hou, Jin-Fu Li, Tsu-Wei Tseng
Memory Built-in Self-Repair Planning Framework for RAMs in SoCs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30 (11) (2011)
Tsu-Wei Tseng, Chih-Sheng Hou, Jin-Fu Li
Automatic generation of memory built-in self-repair circuits in SOCs for minimizing test time and area cost. VTS (2010)
Tsu-Wei Tseng, Jin-Fu Li, Chih-Sheng Hou
A Built-in Method to Repair SoC RAMs in Parallel. IEEE Des. Test Comput. 27 (6) (2010)
Tsu-Wei Tseng, Yu-Jen Huang, Jin-Fu Li
DABISR: A Defect-Aware Built-In Self-Repair Scheme for Single/Multi-Port RAMs in SoCs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (10) (2010)
Jin-Fu Li, Yu-Jen Huang, Yong-Jyun Hu
Testing Random Defect and Process Variation Induced Comparison Faults of TCAMs With Asymmetric Cells. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (11) (2010)
Jin-Fu Li, Cheng-Wen Wu
Is 3D integration an opportunity or just a hype? ASP-DAC (2010)
Che-Wei Chou, Jin-Fu Li, Ji-Jan Chen, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu
A Test Integration Methodology for 3D Integrated Circuits. Asian Test Symposium (2010)
Yu-Jen Huang, Yun-Chao You, Jin-Fu Li
Enhanced IEEE 1500 test wrapper for testing small RAMs in SOCs. SoCC (2010)
Tsu-Wei Tseng, Jin-Fu Li, Chih-Chiang Hsu
ReBISR: A Reconfigurable Built-In Self-Repair Scheme for Random Access Memories in SOCs. IEEE Trans. Very Large Scale Integr. Syst. 18 (6) (2010)
Yu-Jen Huang, Che-Wei Chou, Jin-Fu Li
A low-cost built-in self-test scheme for an array of memories. ETS (2010)
Chun-Chuan Chi, Cheng-Wen Wu, Jin-Fu Li
A low-cost and scalable test architecture for multi-core chips. ETS (2010)
Jin-Fu Li
Testing Comparison and Delay Faults of TCAMs With Asymmetric Cells. IEEE Trans. Very Large Scale Integr. Syst. 18 (6) (2010)
Chih-Sheng Hou, Jin-Fu Li, Che-Wei Chou
Test and Repair Scheduling for Built-In Self-Repair RAMs in SOCs. DELTA (2010)
Jin-Fu Li, Tsu-Wei Tseng, Chih-Sheng Hou
Reliability-Enhancement and Self-Repair Schemes for SRAMs With Static and Dynamic Faults. IEEE Trans. Very Large Scale Integr. Syst. 18 (9) (2010)
Bing-Wei Huang, Jin-Fu Li
Efficient diagnosis algorithms for drowsy SRAMs. ISQED (2009)
Hsing-Chen Lu, Jin-Fu Li
A Programmable Online/Off-line Built-in Self-test Scheme for RAMs with ECC. ISCAS (2009)
Hsiang-Ning Liu, Yu-Jen Huang, Jin-Fu Li
Memory Built-in Self Test in Multicore Chips with Mesh-Based Networks. IEEE Micro 29 (5) (2009)
Yong-Jyun Hu, Yu-Jen Huang, Jin-Fu Li
Modeling and Testing Comparison Faults of TCAMs with Asymmetric Cells. VTS (2009)
Yu-Jen Huang, Jin-Fu Li
Testability Exploration of 3-D RAMs and CAMs. Asian Test Symposium (2009)
Da-Ming Chang, Jin-Fu Li, Yu-Jen Huang
A Built-In Redundancy-Analysis Scheme for Random Access Memories with Two-Level Redundancy. J. Electron. Test. 24 (1-3) (2008)
Hong-Ming Shieh, Jin-Fu Li
A Multi-Code Compression Scheme for Test Time Reduction of System-on-Chip Designs. IEICE Trans. Inf. Syst. (10) (2008)
Tsu-Wei Tseng, Jin-Fu Li
A Shared Parallel Built-In Self-Repair Scheme for Random Access Memories in SOCs. ITC (2008)
Yu-Jen Huang, Jin-Fu Li
A Low-Cost Pipelined BIST Scheme for Homogeneous RAMs in Multicore Chips. ATS (2008)
Chao-Da Huang, Jin-Fu Li, Tsu-Wei Tseng
ProTaR: An Infrastructure IP for Repairing RAMs in System-on-Chips. IEEE Trans. Very Large Scale Integr. Syst. 15 (10) (2007)
Jin-Fu Li
Testing Comparison Faults of Ternary Content Addressable Memories with Asymmetric Cells. ATS (2007)
Jin-Fu Li
Transparent-Test Methodologies for Random Access Memories Without/With ECC. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (10) (2007)
Jin-Fu Li
Testing Ternary Content Addressable Memories With Comparison Faults Using March-Like Tests. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (5) (2007)
Yu-Jen Huang, Jin-Fu Li
Testing ternary content addressable memories with active neighbourhood pattern-sensitive faults. IET Comput. Digit. Tech. 1 (3) (2007)
Jin-Fu Li, Chao-Da Huang
An Efficient Diagnosis Scheme for RAMs with Simple Functional Faults. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2007)
Tsu-Wei Tseng, Chun-Hsien Wu, Yu-Jen Huang, Jin-Fu Li, Alex Pao, Kevin Chiu, Eliot Chen
A Built-In Self-Repair Scheme for Multiport RAMs. VTS (2007)
Hsiang-Huang Wu, Jin-Fu Li, Chi-Feng Wu, Cheng-Wen Wu
CAMEL: An Efficient Fault Simulator with Coupling Fault Simulation Enhancement for CAMs. ATS (2007)
Yao-Xian Yang, Jin-Fu Li, Hsiang-Ning Liu, Chin-Long Wey
Design of cost-efficient memory-based FFT processors using single-port memories. SoCC (2007)
Rei-Fu Huang, Jin-Fu Li, Jen-Chieh Yeh, Cheng-Wen Wu
Raisin: Redundancy Analysis Algorithm Simulation. IEEE Des. Test Comput. 24 (4) (2007)
Jin-Fu Li, Tsu-Wei Tseng, Chin-Long Wey
An Efficient Transparent Test Scheme for Embedded Word-Oriented Memories CoRR (2007)
Jin-Fu Li, Feijun (Frank) Zheng, Kwang-Ting Cheng
Diagnosing scan chains using SAT-based diagnostic pattern generation. SoCC (2007)
Tsu-Wei Tseng, Jin-Fu Li, Da-Ming Chang
A built-in redundancy-analysis scheme for RAMs with 2D redundancy using 1D local bitmap. DATE (2006)
Tsu-Wei Tseng, Jin-Fu Li, Chih-Chiang Hsu, Alex Pao, Kevin Chiu, Eliot Chen
A Reconfigurable Built-In Self-Repair Scheme for Multiple Repairable RAMs in SOCs. ITC (2006)
Yu-Jen Huang, Jin-Fu Li
Testing Active Neighborhood Pattern-Sensitive Faults of Ternary Content Addressable Memories. ETS (2006)
Yu-Jen Huang, Da-Ming Chang, Jin-Fu Li
A Built-In Redundancy-Analysis Scheme for Self-Repairable RAMs with Two-Level Redundancy. DFT (2006)
Jin-Fu Li, Chou-Kun Lin
Modeling and Testing Comparison Faults for Ternary Content Addressable Memories. VTS (2005)

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Publication Activity (10 Years)

Top Topics

Top Venues

Jin-Fu Li