Jiun-Lang Huang

Publication Activity (10 Years)

Years Active: 1997-2023
Publications (10 Years): 18

Top Topics

Semantically Heterogeneous

Pattern Generator

Error Tolerance

Top Venues

J. Electron. Test.

Publications

Hao Cheng, Chi-Jhe Li, Hung-Lin Chen, Jiun-Lang Huang
BDD-Based Self-Test Program Generation for Processor Cores. ITC-Asia (2023)
Iris Hui-Ru Jiang, Yao-Wen Chang, Jiun-Lang Huang, Charlie Chung-Ping Chen
Intelligent Design Automation for Heterogeneous Integration. ISPD (2022)
Jia-Ruei Liang, Ya-Ni Hsieh, Jiun-Lang Huang
Test Response Compaction for Software-Based Self-Test. ITC-Asia (2022)
Iris Hui-Ru Jiang, Yao-Wen Chang, Jiun-Lang Huang, Chung-Ping Chen
Opportunities for 2.5/3D Heterogeneous SoC Integration. VLSI-DAT (2021)
Kai-Hsun Chen, Bo-Yi Yang, Jia-Ruei Liang, Hung-Lin Chen, Jiun-Lang Huang
Automatic Test Program Generation for Transition Delay Faults in Pipelined Processors. ITC-Asia (2021)
Iris Hui-Ru Jiang, Yao-Wen Chang, Jiun-Lang Huang, Chung-Ping Chen
Intelligent Design Automation for 2.5/3D Heterogeneous SoC Integration. ICCAD (2020)
Kuen-Wei Yeh, Jiun-Lang Huang
DSSP-ATPG: A Deterministic Search-Space Parallel Test Pattern Generator. ITC-Asia (2020)
Ching-Yuan Chen, Ching-Hong Cheng, Jiun-Lang Huang, Krishnendu Chakrabarty
Functional-Like Transition Delay Fault Test-Pattern Generation using a Bayesian-Based Circuit Model. ETS (2020)
Kai-Hsun Chen, Ching-Yuan Chen, Jiun-Lang Huang
Testability Measures Considering Circuit Reconvergence to Reduce ATPG Runtime. DDECS (2019)
Ching-Yuan Chen, Jiun-Lang Huang
Reinforcement-Learning-Based Test Program Generation for Software-Based Self-Test. ATS (2019)
Wei-Chen Huang, Guan-Hao Hou, Jiun-Lang Huang, Terry Kuo
An FPGA-Based Data Receiver for Digital IC Testing. ITC-Asia (2019)
Jin-Fu Li, Jiun-Lang Huang
Conference Reports: Report on 2017 IEEE Asian Test Symposium. IEEE Des. Test 35 (2) (2018)
Bo-Yi Li, Jiun-Lang Huang
A Multi-Fault Dynamic Compaction Technique for Test Pattern Count Reduction. ISOCC (2018)
Guan-Hao Hou, Wei-Chen Huang, Jiun-Lang Huang, Terry Kuo
Design and Implementation of an FPGA-Based 16-Channel Data/Timing Formatter. ATS (2018)
Tsung-Yen Tsai, Jiun-Lang Huang
Source code transformation for software-based on-line error detection. DSC (2017)
Yang-Kai Huang, Kuan-Te Li, Chih-Lung Hsiao, Chia-An Lee, Jiun-Lang Huang, Terry Kuo
Design and Implementation of an EG-Pool Based FPGA Formatter with Temperature Compensation. ATS (2017)
Po-Fan Hou, Yi-Tsung Lin, Jiun-Lang Huang, Ann Shih, Zoe F. Conroy
An IR-Drop Aware Test Pattern Generator for Scan-Based At-Speed Testing. ATS (2016)
Kuen-Wei Yeh, Jiun-Lang Huang, Laung-Terng Wang
CPP-ATPG: A Circular Pipeline Processing Based Deterministic Parallel Test Pattern Generator. J. Electron. Test. 32 (5) (2016)
Chun-Hao Chang, Kuen-Wei Yeh, Jiun-Lang Huang, Laung-Terng Wang
SDC-TPG: A Deterministic Zero-Inflation Parallel Test Pattern Generator. ATS (2015)
Tsung-Ching Jim Huang, Jiun-Lang Huang, Kwang-Ting (Tim) Cheng
Design, Automation, and Test for Low-Power and Reliable Flexible Electronics. Found. Trends Electron. Des. Autom. 9 (2) (2015)
Guo-Yu Lin, Kun-Han Tsai, Jiun-Lang Huang, Wu-Tung Cheng
A test-application-count based learning technique for test time reduction. VLSI-DAT (2015)
Yu-Yi Chen, Jiun-Lang Huang, Terry Kuo, Xuan-Lun Huang
Design and Implementation of an FPGA-Based Data/Timing Formatter. J. Electron. Test. 31 (5-6) (2015)
Chung-Yun Wang, Yu-Yi Chen, Jiun-Lang Huang, Xuan-Lun Huang
FPGA-Based Subset Sum Delay Lines. ATS (2014)
Shyue-Kung Lu, Hao-Cheng Jheng, Masaki Hashizume, Jiun-Lang Huang, Pony Ning
Fault Scrambling Techniques for Yield Enhancement of Embedded Memories. Asian Test Symposium (2013)
Shyue-Kung Lu, Huan-Hua Huang, Jiun-Lang Huang, Pony Ning
Synergistic Reliability and Yield Enhancement Techniques for Embedded SRAMs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32 (1) (2013)
Kazunari Enokimoto, Xiaoqing Wen, Kohei Miyase, Jiun-Lang Huang, Seiji Kajihara, Laung-Terng Wang
On Guaranteeing Capture Safety in At-Speed Scan Testing with Broadcast-Scan-Based Test Compression. VLSI Design (2013)
Kuen-Wei Yeh, Jiun-Lang Huang, Hao-Jan Chao, Laung-Terng Wang
A circular pipeline processing based deterministic parallel test pattern generator. ITC (2013)
Hsiu-Ming Chang, Jiun-Lang Huang, Ding-Ming Kwai, Kwang-Ting Cheng, Cheng-Wen Wu
Low-Cost Error Tolerance Scheme for 3-D CMOS Imagers. IEEE Trans. Very Large Scale Integr. Syst. 21 (3) (2013)
Jiun-Lang Huang, Kun-Han Tsai, Yu-Ping Liu, Ruifeng Guo, Manish Sharma, Wu-Tung Cheng
Improve speed path identification with suspect path expressions. VLSI-DAT (2013)
Jiun-Lang Huang, X.-L. Huang, Yung-Fa Chou, Ding-Ming Kwai
A SAR ADC missing-decision level detection and removal technique. VTS (2012)
Shianling Wu, Laung-Terng Wang, Xiaoqing Wen, Wen-Ben Jone, Michael S. Hsiao, Fangfang Li, James Chien-Mo Li, Jiun-Lang Huang
Launch-on-Shift Test Generation for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains. ACM Trans. Design Autom. Electr. Syst. 17 (4) (2012)
Yi-Tsung Lin, Jiun-Lang Huang, Xiaoqing Wen
A Transition Isolation Scan Cell Design for Low Shift and Capture Power. Asian Test Symposium (2012)
Xuan-Lun Huang, Jiun-Lang Huang, Hung-I Chen, Chang-Yu Chen, Tseng Kuo-Tsai, Ming-Feng Huang, Yung-Fa Chou, Ding-Ming Kwai
An MCT-Based Bit-Weight Extraction Technique for Embedded SAR ADC Testing and Calibration. J. Electron. Test. 28 (5) (2012)
Xuan-Lun Huang, Ping-Ying Kang, Jiun-Lang Huang, Yung-Fa Chou, Yung-Pin Lee, Ding-Ming Kwai
A Pre- and Post-bond Self-Testing and Calibration Methodology for SAR ADC Array in 3-D CMOS Imager. ETS (2011)
Xuan-Lun Huang, Ping-Ying Kang, Yuan-Chi Yu, Jiun-Lang Huang
Histogram-Based Calibration of Capacitor Mismatch and Comparator Offset for 1-Bit/Stage Pipelined ADCs. J. Electron. Test. 27 (4) (2011)
Yi-Tsung Lin, Jiun-Lang Huang, Xiaoqing Wen
Clock-gating-aware low launch WSA test pattern generation for at-speed scan testing. ITC (2011)
Shianling Wu, Laung-Terng Wang, Xiaoqing Wen, Zhigang Jiang, Lang Tan, Yu Zhang, Yu Hu, Wen-Ben Jone, Michael S. Hsiao, James Chien-Mo Li, Jiun-Lang Huang, Lizhen Yu
Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30 (3) (2011)
Xuan-Lun Huang, Jiun-Lang Huang
ADC/DAC Loopback Linearity Testing by DAC Output Offsetting and Scaling. IEEE Trans. Very Large Scale Integr. Syst. 19 (10) (2011)
Jiun-Lang Huang, Kwang-Ting (Tim) Cheng
A Promising Alternative to Conventional Silicon. IEEE Des. Test Comput. 28 (6) (2011)
Xuan-Lun Huang, Ping-Ying Kang, Hsiu-Ming Chang, Jiun-Lang Huang, Yung-Fa Chou, Yung-Pin Lee, Ding-Ming Kwai, Cheng-Wen Wu
A self-testing and calibration method for embedded successive approximation register ADC. ASP-DAC (2011)
Tsung-Ching Huang, Jiun-Lang Huang, Kwang-Ting (Tim) Cheng
Robust Circuit Design for Flexible Electronics. IEEE Des. Test Comput. 28 (6) (2011)
Chun-Yong Liang, Meng-Fan Wu, Jiun-Lang Huang
Power Supply Noise Reduction in Broadcast-Based Compression Environment for At-speed Scan Testing. Asian Test Symposium (2010)
Jiun-Lang Huang, Kuo-Yu Chou, Ming-Huan Lu, Xuan-Lun Huang
A robust ADC code hit counting technique. DATE (2010)
Xuan-Lun Huang, Jiun-Lang Huang
An ADC/DAC loopback testing methodology by DAC output offsetting and scaling. VTS (2010)
Meng-Fan Wu, Kun-Han Tsai, Wu-Tung Cheng, Hsin-Cheih Pan, Jiun-Lang Huang, Augusli Kifli
A scalable quantitative measure of IR-drop effects for scan pattern generation. ICCAD (2010)
Hsiu-Ming Chang, Jiun-Lang Huang, Ding-Ming Kwai, Kwang-Ting (Tim) Cheng, Cheng-Wen Wu
An error tolerance scheme for 3D CMOS imagers. DAC (2010)
Meng-Fan Wu, Hsin-Cheih Pan, T.-H. Wang, Jiun-Lang Huang, Kun-Han Tsai, Wu-Tung Cheng
Improved weight assignment for logic switching activity during at-speed test pattern generation. ASP-DAC (2010)
Laung-Terng Wang, Nur A. Touba, Zhigang Jiang, Shianling Wu, Jiun-Lang Huang, James Chien-Mo Li
CSER: BISER-based concurrent soft-error resilience. VTS (2010)
Meng-Fan Wu, Kai-Shun Hu, Jiun-Lang Huang
LPTest: a Flexible Low-Power Test Pattern Generator. J. Electron. Test. 25 (6) (2009)
Meng-Fan Wu, Jiun-Lang Huang, Xiaoqing Wen, Kohei Miyase
Power Supply Noise Reduction for At-Speed Scan Testing in Linear-Decompression Environment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28 (11) (2009)
Chen-Wei Lin, Jiun-Lang Huang
A Charge-Sensing-Capable Source Driver for TFT Array Testing in System-on-Panel Displays. J. Comput. 4 (4) (2009)
Chen-Yuan Yang, Xuan-Lun Huang, Jiun-Lang Huang
An On-Chip Integrator Leakage Characterization Technique and Its Application to Switched Capacitor Circuits Testing. Asian Test Symposium (2009)
Xuan-Lun Huang, Chen-Yuan Yang, Jiun-Lang Huang
Diagnosing integrator leakage of single-bit first-order DeltaSigma modulator using DC input. ASP-DAC (2009)
Chen-Wei Lin, Jiun-Lang Huang
A Built-In TFT Array Charge-Sensing Technique for System-on-Panel Displays. VTS (2008)
Yi-Tsung Lin, Meng-Fan Wu, Jiun-Lang Huang
PHS-Fill: A Low Power Supply Noise Test Pattern Generation Technique for At-Speed Scan Testing in Huffman Coding Test Compression Environment. ATS (2008)
Shianling Wu, Laung-Terng Wang, Zhigang Jiang, Jiayong Song, Boryau Sheu, Xiaoqing Wen, Michael S. Hsiao, James Chien-Mo Li, Jiun-Lang Huang, Ravi Apte
On Optimizing Fault Coverage, Pattern Count, and ATPG Run Time Using a Hybrid Single-Capture Scheme for Testing Scan Designs. DFT (2008)
Meng-Fan Wu, Jiun-Lang Huang, Xiaoqing Wen, Kohei Miyase
Reducing Power Supply Noise in Linear-Decompressor-Based Test Data Compression Environment for At-Speed Scan Testing. ITC (2008)
Jui-Jer Huang, Chiuan-Che Li, Jiun-Lang Huang
Testing LCD Source Driver IC with Built-on-Scribe-Line Test Circuitry. ATS (2008)
Meng-Fan Wu, Kai-Shun Hu, Jiun-Lang Huang
An Efficient Peak Power Reduction Technique for Scan Testing. ATS (2007)
Jiun-Lang Huang
On-Chip Random Jitter Testing Using Low Tap-Count Coarse Delay Lines. J. Electron. Test. 22 (4-6) (2006)
Jiun-Lang Huang, Jui-Jer Huang, Yuan-Shuang Liu
A Low-Cost Jitter Measurement Technique for BIST Applications. J. Electron. Test. 22 (3) (2006)
Jiun-Lang Huang
A Random Jitter Extraction Technique in the Presence of Sinusoidal Jitter. ATS (2006)
Jiun-Lang Huang
Random Jitter Testing Using Low Tap-Count Delay Lines. Asian Test Symposium (2005)
Jui-Jer Huang, Jiun-Lang Huang
An Infrastructure IP for On-Chip Clock Jitter Measurement. ICCD (2004)
Hao-Chiao Hong, Jiun-Lang Huang, Kwang-Ting Cheng, Cheng-Wen Wu, Ding-Ming Kwai
Practical considerations in applying Σ-Δ modulation-based analog BIST to sampled-data systems. IEEE Trans. Circuits Syst. II Express Briefs 50 (9) (2003)
Jui-Jer Huang, Jiun-Lang Huang
A Low-Cost Jitter Measurement Technique for BIST Applications. Asian Test Symposium (2003)
Hao-Chiao Hong, Jiun-Lang Huang, Kwang-Ting Cheng, Cheng-Wen Wu
On-chip Analog Response Extraction with 1-Bit ? - Modulators. Asian Test Symposium (2002)
Jiun-Lang Huang, Kwang-Ting Cheng
An On-Chip Short-Time Interval Measurement Technique for Testing High-Speed Communication Links. VTS (2001)
Jan Arild Tofte, Chee-Kian Ong, Jiun-Lang Huang, Kwang-Ting (Tim) Cheng
Characterization of a Pseudo-Random Testing Technique for Analog and Mixed-Signal Built-in-Self-Test. VTS (2000)
Jiun-Lang Huang, Kwang-Ting Cheng
Testing and characterization of the one-bit first-order delta-sigma modulator for on-chip analog signal analysis. ITC (2000)
Jiun-Lang Huang, Kwang-Ting Cheng
A sigma-delta modulation based BIST scheme for mixed-signal circuits. ASP-DAC (2000)
Jiun-Lang Huang, Chee-Kian Ong, Kwang-Ting Cheng
A BIST Scheme for On-Chip ADC and DAC Testing. DATE (2000)
Jiun-Lang Huang, Chen-Yang Pan, Kwang-Ting Cheng
Specification Back-Propagation and Its Application to DC Fault Simulation for Analog/Mixed-Signal Circuits. VTS (1999)
Jiun-Lang Huang, Kwang-Ting Cheng
Analog Fault Diagnosis for Unpowered Circuit Boards. ITC (1997)