James Chien-Mo Li

Publication Activity (10 Years)

Years Active: 2005-2024
Publications (10 Years): 32

Top Topics

Jacobian Matrix

Pattern Generation

Analog Circuits

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

Publications

Cheng-Yun Hsieh, Hsin-Ying Tsai, Yuan-Hsiang Lu, James Chien-Mo Li
Small Sampling Overhead Error Mitigation for Quantum Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43 (3) (2024)
Xin-Ping Chen, Hsu-Yu Huang, Chu-Yun Hsiao, Jennifer Shueh-Inn Hu, James Chien-Mo Li
Test Compression for Neuromorphic Chips. ETS (2024)
Bing-Han Hsieh, Yun-Sheng Liu, James Chien-Mo Li, Chris Nigh, Mason Chern, Gaurav Bhargava
Diagnosis of Systematic Delay Failures Through Subset Relationship Analysis. ITC (2023)
Yu-Min Li, Cheng-Yun Hsieh, Yen-Wei Li, James Chien-Mo Li
Diagnosis of Quantum Circuits in the NISQ Era. VTS (2023)
Zhe-Jia Liang, Yu-Tsung Wu, Yun-Feng Yang, James Chien-Mo Li, Norman Chang, Akhilesh Kumar, Ying-Shiun Li
High-Speed, Low-Storage Power and Thermal Predictions for ATPG Test Patterns. ITC (2023)
Chun Chen, Jeng-Yu Liao, James Chien-Mo Li, Harry H. Chen, Eric Jia-Wei Fang
Vmin Prediction Using Nondestructive Stress Test. VTS (2023)
Wei-Chen Lin, Chun Chen, Chao-Ho Hsieh, James Chien-Mo Li, Eric Jia-Wei Fang, Sung S.-Y. Hsueh
ML-Assisted VminBinning with Multiple Guard Bands for Low Power Consumption. ITC (2022)
I-Wei Chiu, Xin-Ping Chen, Jennifer Shueh-Inn Hu, James Chien-Mo Li
Automatic Test Configuration and Pattern Generation (ATCPG) for Neuromorphic Chips. ICCAD (2022)
Cheng-Sian Kuo, Bing-Han Hsieh, James Chien-Mo Li, Chris Nigh, Gaurav Bhargava, Mason Chern
Diagnosing Double Faulty Chains through Failing Bit Separation. ITC (2022)
Yi-Zhan Hsieh, Hsiao-Yin Tseng, I-Wei Chiu, James Chien-Mo Li
Fault Modeling and Testing of Spiking Neural Network Chips. ITC-Asia (2021)
Yen-Ting Kuo, Wei-Chen Lin, Chun Chen, Chao-Ho Hsieh, James Chien-Mo Li, Eric Jia-Wei Fang, Sung S.-Y. Hsueh
Minimum Operating Voltage Prediction in Production Test Using Accumulative Learning. ITC (2021)
Hsiao-Yin Tseng, I-Wei Chiu, Mu-Ting Wu, James Chien-Mo Li
Machine Learning-Based Test Pattern Generation for Neuromorphic Chips. ICCAD (2021)
Mu-Ting Wu, Cheng-Sian Kuo, James Chien-Mo Li, Chris Nigh, Gaurav Bhargava
Improving Volume Diagnosis and Debug with Test Failure Clustering and Reorganization. ITC (2021)
Cheng-Yun Hsieh, Chen-Hung Wu, Chia-Hsien Huang, His-Sheng Goan, James Chien-Mo Li
Realistic Fault Models and Fault Simulation for Quantum Dot Quantum Circuits. DAC (2020)
Ming-Ting Lee, Chen-Hung Wu, Shi-Tang Liu, Cheng-Yun Hsieh, James Chien-Mo Li
High Efficiency and Low Overkill Testing for Probabilistic Circuits. ITC-Asia (2020)
Chih-Yan Liu, Mu-Ting Wu, James Chien-Mo Li, Gaurav Bhargava, Chris Nigh
Systematic Hold-time Fault Diagnosis and Failure Debug in Production Chips. ATS (2020)
Chen-Hung Wu, Cheng-Yun Hsieh, Jiun-Yun Li, James Chien-Mo Li
qATG: Automatic Test Generation for Quantum Circuits. ITC (2020)
Yan-Shen You, Chih-Yan Liu, Mu-Ting Wu, Po-Wei Chen, James Chien-Mo Li
Diagnosis technique for Clustered Multiple Transition Delay Faults. ITC-Asia (2020)
Kai-Chieh Yang, Ming-Ting Lee, Chen-Hung Wu, James Chien-Mo Li
ATPG and Test Compression for Probabilistic Circuits. VLSI-DAT (2019)
Shih-An Hsieh, Ying-Hsu Wang, Ting-Yu Shen, Kuan-Yen Huang, Chia-Cheng Pai, Tsai-Chieh Chen, James Chien-Mo Li
DR-Scan: Dual-Rail Asynchronous Scan DfT and ATPG. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38 (1) (2019)
Run-Yi Wang, Chia-Cheng Pai, Jun-Jie Wang, Hsiang-Ting Wen, Yu-Cheng Pai, Yao-Wen Chang, James Chien-Mo Li, Jie-Hong Roland Jiang
Efficient multi-layer obstacle-avoiding region-to-region rectilinear steiner tree construction. DAC (2018)
Ting-Yu Shen, Chia-Cheng Pai, Tsai-Chieh Chen, James Chien-Mo Li, Samuel Pan
Test methodology for PCHB/PCFB Asynchronous Circuits. ITC (2018)
Yu-Wei Chen, Yu-Hao Ho, Chih-Ming Chang, Kai-Chieh Yang, Ming-Ting Li, James Chien-Mo Li
Parallel order ATPG for test compaction. VLSI-DAT (2018)
Runqing Cao, James Chien-Mo Li, Lei Zuo, Zeyu Wang, Yunlong Lu
A new method for parameter estimation of high-order polynomial-phase signals. Signal Process. 142 (2018)
Yu-Ching Li, Shih-Yao Lin, Heng-Yi Lin, James Chien-Mo Li
Diagnosis and repair of cells (DRC) responsible for power-supply-noise violations. VLSI-DAT (2018)
Yu-Hao Ho, Yo-Wei Chen, Chih-Ming Chang, Kai-Chieh Yang, James Chien-Mo Li
Robust test pattern generation for hold-time faults in nanometer technologies. VLSI-DAT (2017)
Po-Hao Chen, Chi-Lin Lee, Jing-Yu Chen, Po-Wei Chen, James Chien-Mo Li
Physical-aware diagnosis of multiple interconnect defects. ITC-Asia (2017)
Yu-Cheng Liu, Cheng-Yu Han, Shih-Ya Lin, James Chien-Mo Li
PSN-aware circuit test timing prediction using machine learning. IET Comput. Digit. Tech. 11 (2) (2017)
Chih-Ming Chang, Kai-Jie Yang, James Chien-Mo Li, Hung Chen
Test Pattern Compression for Probabilistic Circuits. ATS (2017)
Cheng-Yu Han, Yu-Ching Li, Hao-Tien Kan, James Chien-Mo Li
Power-Supply-Noise-Aware Timing Analysis and Test Pattern Regeneration. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2016)
Hung-I Lee, Chen-Yo Han, James Chien-Mo Li
A Multicircuit Simulator Based on Inverse Jacobian Matrix Reuse. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35 (7) (2016)
Wei-Sheng Ding, Hung-Yi Hsieh, Cheng-Yu Han, James Chien-Mo Li, Xiaoqing Wen
Test Pattern Modification for Average IR-Drop Reduction. IEEE Trans. Very Large Scale Integr. Syst. 24 (1) (2016)
Kuan-Ying Chiang, Yu-Hao Ho, Yo-Wei Chen, Cheng-Sheng Pan, James Chien-Mo Li
Fault Simulation and Test Pattern Generation for Cross-gate Defects in FinFET Circuits. ATS (2015)
Ang-Feng Lin, Kuan-Yu Liao, Kuan-Ying Chiang, James Chien-Mo Li
TARGET: Timing-AwaRe Gate Exhaustive Transition ATPG for cell-internal defects. VLSI-DAT (2015)
Kuan-Yu Liao, Po-Juei Chen, Ang-Feng Lin, James Chien-Mo Li, Michael S. Hsiao, Laung-Terng Wang
GPU-based timing-aware test generation for small delay defects. ETS (2014)
Ming-Hong Tsai, Wei-Sheng Ding, Hung-Yi Hsieh, James Chien-Mo Li
Transient IR-Drop Analysis for At-Speed Testing Using Representative Random Walk. IEEE Trans. Very Large Scale Integr. Syst. 22 (9) (2014)
Chun-Yi Kuo, Chi-Jih Shih, Yi-Chang Lu, James Chien-Mo Li, Krishnendu Chakrabarty
Testing of TSV-Induced Small Delay Faults for 3-D Integrated Circuits. IEEE Trans. Very Large Scale Integr. Syst. 22 (3) (2014)
Shih-Min Chao, Po-Juei Chen, Jing-Yu Chen, Po-Hao Chen, Ang-Feng Lin, James Chien-Mo Li, Pei-Ying Hsueh, Chun-Yi Kuo, Ying-Yen Chen, Jih-Nung Li
Divide and conquer diagnosis for multiple defects. ITC (2014)
Yen-Lung Chen, Wan-Rong Wu, Chien-Nan Jimmy Liu, James Chien-Mo Li
Simultaneous Optimization of Analog Circuits With Reliability and Variability for Applications on Flexible Electronics. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33 (1) (2014)
Chi-Jih Shih, Shih-An Hsieh, Yi-Chang Lu, James Chien-Mo Li, Tzong-Lin Wu, Krishnendu Chakrabarty
Test Generation of Path Delay Faults Induced by Defects in Power TSV. Asian Test Symposium (2013)
Kuan-Yu Liao, Sheng-Chang Hsu, James Chien-Mo Li
GPU-based n-detect transition fault ATPG. DAC (2013)
Bing-Chuan Bai, Chun-Lung Hsu, Ming-Hsueh Wu, Chen-An Chen, Yee-Wen Chen, Kun-Lun Luo, Liang-Chia Cheng, James Chien-Mo Li
Back-End-of-Line Defect Analysis for Rnv8T Nonvolatile SRAM. Asian Test Symposium (2013)
Chia-Yuan Chang, Kuan-Yu Liao, Sheng-Chang Hsu, James Chien-Mo Li, Jiann-Chyi Rau
Compact Test Pattern Selection for Small Delay Defect. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32 (6) (2013)
Geng-Ming Chiu, James Chien-Mo Li
A Secure Test Wrapper Design Against Internal and Boundary Scan Attacks for Embedded Cores. IEEE Trans. Very Large Scale Integr. Syst. 20 (1) (2012)
Chih-Yao Hsu, Chun-Yi Kuo, James Chien-Mo Li, Krishnendu Chakrabarty
3D IC test scheduling using simulated annealing. VLSI-DAT (2012)
Wei-Lin Tsai, Wei-Chih Liu, James Chien-Mo Li
Structural Reduction Techniques for Logic-Chain Bridging Fault Diagnosis. IEEE Trans. Computers 61 (7) (2012)
Shianling Wu, Laung-Terng Wang, Xiaoqing Wen, Wen-Ben Jone, Michael S. Hsiao, Fangfang Li, James Chien-Mo Li, Jiun-Lang Huang
Launch-on-Shift Test Generation for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains. ACM Trans. Design Autom. Electr. Syst. 17 (4) (2012)
Yu-Shun Wang, Min-Han Hsieh, James Chien-Mo Li, Charlie Chung-Ping Chen
An At-Speed Test Technique for High-Speed High-order Adder by a 6.4-GHz 64-bit Domino Adder Example. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2012)
Kuan-Yu Liao, Chia-Yuan Chang, James Chien-Mo Li
A Parallel Test Pattern Generation Algorithm to Meet Multiple Quality Objectives. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30 (11) (2011)
Po-Juei Chen, Wei-Li Hsu, James Chien-Mo Li, Nan-Hsin Tseng, Kuo-Yin Chen, Wei-pin Changchien, Charles C. C. Liu
An Accurate Timing-Aware Diagnosis Algorithm for Multiple Small Delay Defects. Asian Test Symposium (2011)
Chi-Hsuan Cheng, James Chien-Mo Li
An Asynchronous Design for Testability and Implementation in Thin-film Transistor Technology. J. Electron. Test. 27 (2) (2011)
Jen-Yang Wen, Yu-Chuan Huang, Min-Hong Tsai, Kuan-Yu Liao, James Chien-Mo Li, Ming-Tung Chang, Min-Hsiu Tsai, Chih-Mou Tseng, Hung-Chun Li
Test clock domain optimization for peak power supply noise reduction during scan. ITC (2011)
Yu-Shun Wang, Min-Han Hsieh, Chia-Ming Liu, Chi-Wei Liu, James Chien-Mo Li, Charlie Chung-Ping Chen
An at-speed self-testable technique for the high speed domino adder. CICC (2011)
Shianling Wu, Laung-Terng Wang, Xiaoqing Wen, Zhigang Jiang, Lang Tan, Yu Zhang, Yu Hu, Wen-Ben Jone, Michael S. Hsiao, James Chien-Mo Li, Jiun-Lang Huang, Lizhen Yu
Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30 (3) (2011)
W.-C. Wang, C.-Y. Hsu, James Chien-Mo Li, Y.-C. Sung, A. Rao, L.-T. Wang
Row-linear feedback shift register-column x-masking technique for simultaneous testing of many-core system chips. IET Comput. Digit. Tech. 5 (4) (2011)
Chao-Hsuan Hsu, Chester Liu, En-Hua Ma, James Chien-Mo Li
Static timing analysis for flexible TFT circuits. DAC (2010)
Laung-Terng Wang, Nur A. Touba, Zhigang Jiang, Shianling Wu, Jiun-Lang Huang, James Chien-Mo Li
CSER: BISER-based concurrent soft-error resilience. VTS (2010)
F.-M. Wang, W.-C. Wang, James Chien-Mo Li
Time-space test response compaction and diagnosis based on BCH codes. IET Comput. Digit. Tech. 3 (3) (2009)
Tzuo-Fan Chien, Wen-Chi Chao, James Chien-Mo Li, Yao-Wen Chang, Kuan-Yu Liao, Ming-Tung Chang, Min-Hsiu Tsai, Chih-Mou Tseng
BIST design optimization for large-scale embedded memory cores. ICCAD (2009)
Shiue-Tsung Shen, Wei-Hsiao Liu, En-Hua Ma, James Chien-Mo Li, I-Chun Cheng
Very-Low-Voltage Testing of Amorphous Silicon TFT Circuits. Asian Test Symposium (2009)
Po-Juei Chen, James Chien-Mo Li, Hsing Jasmine Chao
Bridging Fault Diagnosis to Identify the Layer of Systematic Defects. Asian Test Symposium (2009)
James Chien-Mo Li, Po-Chou Lin, Chih-Ming Chiang, Chuo-Jan Pan, Chao-Wen Tseng
Effective and Economic Phase Noise Testing for Single-Chip TV Tuners. IEEE Trans. Instrum. Meas. 57 (10) (2008)
Wei-Shun Chuang, Shiu-Ting Lin, Wei-Chih Liu, James Chien-Mo Li
Diagnosis of Multiple Scan Chain Timing Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27 (6) (2008)
Wei-Chih Liu, Wei-Lin Tsai, Hsiu-Ting Lin, James Chien-Mo Li
Diagnosis of Logic-to-chain Bridging Faults. ITC (2008)
Yu Huang, Ruifeng Guo, Wu-Tung Cheng, James Chien-Mo Li
Survey of Scan Chain Diagnosis. IEEE Des. Test Comput. 25 (3) (2008)
Shianling Wu, Laung-Terng Wang, Zhigang Jiang, Jiayong Song, Boryau Sheu, Xiaoqing Wen, Michael S. Hsiao, James Chien-Mo Li, Jiun-Lang Huang, Ravi Apte
On Optimizing Fault Coverage, Pattern Count, and ATPG Run Time Using a Hybrid Single-Capture Scheme for Testing Scan Designs. DFT (2008)
Yu-Te Liaw, Bing-Chuan Bai, James Chien-Mo Li
A Two-level Simultaneous Test Data and Time Reduction Technique for SOC. J. Inf. Sci. Eng. 24 (3) (2008)
Geng-Ming Chiu, James Chien-Mo Li
IEEE 1500 Compatible Secure Test Wrapper For Embedded IP Cores. ITC (2008)
Chun-Yi Lee, Hung-Mao Lin, Fang-Min Wang, James Chien-Mo Li
Cyclic-CPRS : A Diagnosis Technique for BISTed Circuits for Nano-meter Technologies. ASP-DAC (2007)
James Chien-Mo Li, Hung-Mao Lin, Fang-Min Wang
Column Parity Row Selection (CPRS) BIST Diagnosis Technique: Modeling and Analysis. IEEE Trans. Computers 56 (3) (2007)
Chun-Yi Lee, James Chien-Mo Li
Design and Chip Implementation of the Segment Weighted Random BIST for Low Power Testing. J. Low Power Electron. 3 (2) (2007)
Yu-Long Kao, Wei-Shun Chuang, James Chien-Mo Li
Jump Simulation: A Technique for Fast and Precise Scan Chain Fault Diagnosis. ITC (2006)
James Chien-Mo Li
Diagnosis of Timing Faults in Scan Chains Using Single Excitation Patterns. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (4) (2005)
Hung-Mao Lin, James Chien-Mo Li
Column parity and row selection (CPRS): a BIST diagnosis technique for multiple errors in multiple scan chains. ITC (2005)
James Chien-Mo Li
Diagnosis of Multiple Hold-Time and Setup-Time Faults in Scan Chains. IEEE Trans. Computers 54 (11) (2005)
James Chien-Mo Li
Diagnosis of single stuck-at faults and multiple timing faults in scan chains. IEEE Trans. Very Large Scale Integr. Syst. 13 (6) (2005)