Yu Huang

Publication Activity (10 Years)

Years Active: 2000-2021
Publications (10 Years): 16

Top Topics

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Supervised Machine Learning

Reasoning Process

Top Venues

Publications

Yu Huang, David Francis, Yervant Zorian, Nilanjan Mukherjee
Automotive Test and Reliability. ITC-Asia (2021)
Huawei Li, Xiaowei Li, Yu Huang, Ying Wang, Gary Guo
Special Session - Test for AI Chips: from DFT to On-line Testing. VTS (2021)
Yu Huang, Wu-Tung Cheng, Ruifeng Guo, Sameer Chillarige
Diagnosis and Yield Learning. ITC-Asia (2021)
Mason Chern, Shih-Wei Lee, Shi-Yu Huang, Yu Huang, Gaurav Veda, Kun-Han Tsai, Wu-Tung Cheng
Diagnosis of Intermittent Scan Chain Faults Through a Multistage Neural Network Reasoning Process. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (10) (2020)
Fong-Jyun Tsai, Chong-Siao Ye, Yu Huang, Kuen-Jong Lee, Wu-Tung Cheng, Sudhakar M. Reddy, Mark Kassab, Janusz Rajski, Shi-Xuan Zheng
Estimation of Test Data Volume for Scan Architectures with Different Numbers of Input Channels. ITC-Asia (2020)
Yu Huang, Janusz Rajski, Mark Kassab, Nilanjan Mukherjee, Jeffrey Mayer
Effective Design of Layout-Friendly EDT Decompressor. VTS (2020)
Fong-Jyun Tsai, Chong-Siao Ye, Yu Huang, Kuen-Jong Lee, Wu-Tung Cheng, Sudhakar M. Reddy, Mark Kassab, Janusz Rajski
Efficient Prognostication of Pattern Count with Different Input Compression Ratios. ETS (2020)
Yu Huang, Sylwester Milewski, Janusz Rajski, Jerzy Tyszer, Chen Wang
Low Cost Hypercompression of Test Data. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (10) (2020)
Fong-Jyun Tsai, Chong-Siao Ye, Kuen-Jong Lee, Shi-Xuan Zheng, Yu Huang, Wu-Tung Cheng, Sudhakar M. Reddy, Mark Kassab, Janusz Rajski, Chen Wang, Justyna Zawada
Prediction of Test Pattern Count and Test Data Volume for Scan Architectures under Different Input Channel Configurations. ITC (2020)
Yu Huang, Szczepan Urban, Wu-Tung Cheng, Manish Sharma, Fengju Niu, Junna Zhong, Wen-Lung Hsu
Reversible Scan Based Diagnostic Patterns. VLSI-DAT (2019)
Yu Huang, Jakub Janicki, Szczepan Urban
Non-Adaptive Pattern Reordering to Improve Scan Chain Diagnostic Resolution. ETS (2019)
Cheng-Hung Wu, Yu Huang, Kuen-Jong Lee, Wu-Tung Cheng, Gaurav Veda, Sudhakar M. Reddy, Chun-Cheng Hu, Chong-Siao Ye
Deep Learning Based Test Compression Analyzer. ATS (2019)
Mason Chern, Shih-Wei Lee, Shi-Yu Huang, Yu Huang, Gaurav Veda, Kun-Han Hans Tsai, Wu-Tung Cheng
Improving scan chain diagnostic accuracy using multi-stage artificial neural networks. ASP-DAC (2019)
Yu Huang, Sylwester Milewski, Janusz Rajski, Jerzy Tyszer, Chen Wang
Hypercompression of Test Patterns. ITC (2018)
Yu Huang, Brady Benware, Randy Klingenberg, Huaxing Tang, Jayant Dsouza, Wu-Tung Cheng
Scan Chain Diagnosis Based on Unsupervised Machine Learning. ATS (2017)
Yu Huang, Wu-Tung Cheng
On designing two-dimensional scan architecture for test chips. VLSI-DAT (2017)
Jing Ye, Yu Huang, Yu Hu, Wu-Tung Cheng, Ruifeng Guo, Liyang Lai, Ting-Pu Tai, Xiaowei Li, Wei-pin Changchien, Daw-Ming Lee, Ji-Jan Chen, Sandeep C. Eruvathi, Kartik K. Kumara, Charles C. C. Liu, Sam Pan
Diagnosis and Layout Aware (DLA) Scan Chain Stitching. IEEE Trans. Very Large Scale Integr. Syst. 23 (3) (2015)
Yu Huang, Wu Yang, Wu-Tung Cheng
Advancements in diagnosis driven yield analysis (DDYA): A survey of state-of-the-art scan diagnosis and yield analysis technologies. ETS (2015)
Wu-Tung Cheng, Yan Dong, Grady Giles, Yu Huang, Jakub Janicki, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
Scan Test Bandwidth Management for Ultralarge-Scale System-on-Chip Architectures. IEEE Trans. Very Large Scale Integr. Syst. 23 (6) (2015)
Guoliang Li, Jun Qian, Qinfu Yang, Yuan Zuo, Rui Li, Yu Huang, Mark Kassab, Janusz Rajski
Hybrid Hierarchical and Modular Tests for SoC Designs. NATW (2015)
Jing Ye, Yu Hu, Xiaowei Li, Wu-Tung Cheng, Yu Huang, Huaxing Tang
Diagnose Failures Caused by Multiple Locations at a Time. IEEE Trans. Very Large Scale Integr. Syst. 22 (4) (2014)
Kan Xiao, Md. Tauhidur Rahman, Domenic Forte, Yu Huang, Mei Su, Mohammad Tehranipoor
Bit selection algorithm suitable for high-volume production of SRAM-PUF. HOST (2014)
Yu Huang, Mark Kassab, Jay Jahangiri, Janusz Rajski, Wu-Tung Cheng, Dongkwan Han, Jihye Kim, Kun Young Chung
Test Compression Improvement with EDT Channel Sharing in SoC Designs. NATW (2014)
Jakub Janicki, Jerzy Tyszer, Wu-Tung Cheng, Yu Huang, Mark Kassab, Nilanjan Mukherjee, Janusz Rajski, Yan Dong, Grady Giles
EDT bandwidth management - Practical scenarios for large SoC designs. ITC (2013)
Jing Ye, Yu Huang, Yu Hu, Wu-Tung Cheng, Ruifeng Guo, Liyang Lai, Ting-Pu Tai, Xiaowei Li, Wei-pin Changchien, Daw-Ming Lee, Ji-Jan Chen, Sandeep C. Eruvathi, Kartik K. Kumara, Charles C. C. Liu, Sam Pan
Diagnosis and Layout Aware (DLA) scan chain stitching. ITC (2013)
Yu Huang, Xiaoxin Fan, Huaxing Tang, Manish Sharma, Wu-Tung Cheng, Brady Benware, Sudhakar M. Reddy
Distributed dynamic partitioning based diagnosis of scan chain. VTS (2013)
Jianbo Li, Yu Huang, Wu-Tung Cheng, Chris Schuermyer, Dong Xiang, Eric Faehn, Ruth Farrugia
A Hybrid Flow for Memory Failure Bitmap Classification. Asian Test Symposium (2012)
Xiaoxin Fan, Huaxing Tang, Yu Huang, Wu-Tung Cheng, Sudhakar M. Reddy, Brady Benware
Improved volume diagnosis throughput using dynamic design partitioning. ITC (2012)
Yu Huang, Brady Benware, Wu-Tung Cheng, Ting-Pu Tai, Feng-Ming Kuo, Yuan-Shih Chen
Case study of scan chain diagnosis and PFA on a low yield wafer. ITC (2010)
Wu-Tung Cheng, Yu Huang
Enhance Profiling-Based Scan Chain Diagnosis by Pattern Masking. Asian Test Symposium (2010)
Ke Peng, Yu Huang, Ruifeng Guo, Wu-Tung Cheng, Mohammad Tehranipoor
Emulating and diagnosing IR-drop by using dynamic SDF. ASP-DAC (2010)
Ke Peng, Yu Huang, Pinki Mallick, Wu-Tung Cheng, Mohammad Tehranipoor
Full-circuit SPICE simulation based validation of dynamic delay estimation. ETS (2010)
Kun-Han Tsai, Yu Huang, Wu-Tung Cheng, Ting-Pu Tai, Augusli Kifli
Test cycle power optimization for scan-based designs. ITC (2010)
Elif Alpaslan, Yu Huang, Xijiang Lin, Wu-Tung Cheng, Jennifer Dworak
On Reducing Scan Shift Activity at RTL. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (7) (2010)
Xun Tang, Ruifeng Guo, Wu-Tung Cheng, Sudhakar M. Reddy, Yu Huang
On Improving Diagnostic Test Generation for Scan Chain Failures. Asian Test Symposium (2009)
Yu Huang, Wu-Tung Cheng, Ruifeng Guo, Ting-Pu Tai, Feng-Ming Kuo, Yuan-Shih Chen
Scan Chain Diagnosis by Adaptive Signal Profiling with Manufacturing ATPG Patterns. Asian Test Symposium (2009)
Fei Wang, Yu Hu, Yu Huang, Jing Ye, Xiaowei Li
Observation Point Oriented Deterministic Diagnosis Pattern Generation (DDPG) for Chain Diagnosis. ATS (2008)
Xijiang Lin, Yu Huang
Scan Shift Power Reduction by Freezing Power Sensitive Scan Cells. J. Electron. Test. 24 (4) (2008)
Ruifeng Guo, Liyang Lai, Yu Huang, Wu-Tung Cheng
Detection and Diagnosis of Static Scan Cell Internal Defect. ITC (2008)
Fei Wang, Yu Hu, Huawei Li, Xiaowei Li, Jing Ye, Yu Huang
Deterministic Diagnostic Pattern Generation (DDPG) for Compound Defects. ITC (2008)
Yu Huang, Wu-Tung Cheng, Ruifeng Guo
Diagnose Multiple Stuck-at Scan Chain Faults. ETS (2008)
Yu Huang, Ruifeng Guo, Wu-Tung Cheng, James Chien-Mo Li
Survey of Scan Chain Diagnosis. IEEE Des. Test Comput. 25 (3) (2008)
Elif Alpaslan, Yu Huang, Xijiang Lin, Wu-Tung Cheng, Jennifer Dworak
Reducing Scan Shift Power at RTL. VTS (2008)
Yu Huang
Dynamic learning based scan chain diagnosis. DATE (2007)
Ruifeng Guo, Yu Huang, Wu-Tung Cheng
Fault Dictionary Based Scan Chain Failure Diagnosis. ATS (2007)
Yu Huang, Wu-Tung Cheng, Ruifeng Guo, Will Hsu, Yuan-Shih Chen, Albert Mann
Diagnose compound scan chain and system logic defects. ITC (2007)
Yu Huang, Nilanjan Mukherjee, Wu-Tung Cheng, Greg Aldrich
A RTL Testability Analyzer Based on Logical Virtual Prototyping. ATS (2007)
Wu Yang, Wu-Tung Cheng, Yu Huang, Martin Keim, Randy Klingenberg
Scan Diagnosis and Its Successful Industrial Applications. ATS (2007)
Yu Huang, Xijiang Lin
Programmable Logic BIST for At-speed Test. ATS (2007)
Chunsheng Liu, Yang Wu, Yu Huang
Effect of IR-Drop on Path Delay Testing Using Statistical Analysis. ATS (2007)
Chunsheng Liu, Yu Huang
Effects of Embedded Decompression and Compaction Architectures on Side-Channel Attack Resistance. VTS (2007)
Ruifeng Guo, Yu Huang, Wu-Tung Cheng
A complete test set to diagnose scan chain failures. ITC (2007)
Yu Huang, Keith Gallie
Diagnosis of defects on scan enable and clock trees. DATE (2006)
Yu Huang
On N-Detect Pattern Set Optimization. ISQED (2006)
Yu Huang, Wu-Tung Cheng, Nagesh Tamarapalli, Janusz Rajski, Randy Klingenberg, Will Hsu, Yuan-Shih Chen
Diagnosis with Limited Failure Information. ITC (2006)
Yu Huang, Wu-Tung Cheng, Janusz Rajski
Compressed pattern diagnosis for scan chain failures. ITC (2005)
Yu Huang, Wu-Tung Cheng, Greg Crowell
Using fault model relaxation to diagnose real scan chain defects. ASP-DAC (2005)
Yu Huang
Off-shore outsource DFT vs. build off-shore branch offices. ITC (2005)
Yu Huang, Wu-Tung Cheng, Cheng-Ju Hsieh, Huan-Yung Tseng, Alou Huang, Yu-Ting Hung
Intermittent Scan Chain Fault Diagnosis Based on Signal Probability Analysis. DATE (2004)
Wu-Tung Cheng, Kun-Han Tsai, Yu Huang, Nagesh Tamarapalli, Janusz Rajski
Compactor Independent Direct Diagnosis. Asian Test Symposium (2004)
Yu Huang, Wu-Tung Cheng
Using embedded infrastructure IP for SOC post-silicon verification. DAC (2003)
Yu Huang, Wu-Tung Cheng, Sudhakar M. Reddy, Cheng-Ju Hsieh, Yu-Ting Hung
Statistical Diagnosis for Intermittent Scan Chain Hold-Time Fault. ITC (2003)
Yu Huang, Wu-Tung Cheng, Chien-Chung Tsai, Nilanjan Mukherjee, Sudhakar M. Reddy
Static Pin Mapping and SOC Test Scheduling for Cores with Multiple Test Sets. ISQED (2003)
Yu Huang, Wu-Tung Cheng, Cheng-Ju Hsieh, Huan-Yung Tseng, Alou Huang, Yu-Ting Hung
Efficient Diagnosis for Multiple Intermittent Scan Chain Hold-Time Faults. Asian Test Symposium (2003)
Wei Zou, Sudhakar M. Reddy, Irith Pomeranz, Yu Huang
SOC Test Scheduling Using Simulated Annealing. VTS (2003)
Yu Huang, Sudhakar M. Reddy, Wu-Tung Cheng, Paul Reuter, Nilanjan Mukherjee, Chien-Chung Tsai, Omer Samman, Yahya Zaidan
Optimal Core Wrapper Width Selection and SOC Test Scheduling Based on 3-D Bin Packing Algorithm. ITC (2002)
Yu Huang, Chien-Chung Tsai, Nilanjan Mukherjee, Omer Samman, Wu-Tung Cheng, Sudhakar M. Reddy
Synthesis of Scan Chains for Netlist Descriptions at RT-Level. J. Electron. Test. 18 (2) (2002)
Yu Huang, Wu-Tung Cheng, Chien-Chung Tsai, Nilanjan Mukherjee, Omer Samman, Yahya Zaidan, Sudhakar M. Reddy
On Concurrent Test of Core-Based SOC Design. J. Electron. Test. 18 (4-5) (2002)
Yu Huang, Nilanjan Mukherjee, Chien-Chung Tsai, Omer Samman, Yahya Zaidan, Yanping Zhang, Wu-Tung Cheng, Sudhakar M. Reddy
Constraint Driven Pin Mapping for Concurrent SOC Testing. VLSI Design (2002)
Yu Huang, Sudhakar M. Reddy, Wu-Tung Cheng
Core - Clustering Based SOC Test Scheduling Optimization. Asian Test Symposium (2002)
Yu Huang, Chien-Chung Tsai, Nilanjan Mukherhee, Wu-Tung Cheng, Sudhakar M. Reddy
Effect of RTL coding style on testability. CICC (2001)
Yu Huang, Wu-Tung Cheng, Chien-Chung Tsai, Nilanjan Mukherjee, Omer Samman, Yahya Zaidan, Sudhakar M. Reddy
Resource Allocation and Test Scheduling for Concurrent Test of Core-Based SoC D. Asian Test Symposium (2001)
Yu Huang, Chien-Chung Tsai, Nilanjan Mukherjee, Omer Samman, Dan Devries, Wu-Tung Cheng, Sudhakar M. Reddy
On RTL scan design. ITC (2001)
Yu Huang, Irith Pomeranz, Sudhakar M. Reddy, Janusz Rajski
Improving the Proportion of At-Speed Tests in Scan BIST. ICCAD (2000)