Nagesh Tamarapalli

Publication Activity (10 Years)

Years Active: 1996-2015
Publications (10 Years): 0

Top Topics

Causal Reasoning

Conducted An Empirical Study

Multiple Faults

Top Venues

Publications

Nagesh Tamarapalli, Prashanth Vallur, Sachin Kulkarni
Tutorial T5: High Performance Low Power Designs - Challenges and Best practices in Design, Verification and Test. VLSI Design (2015)
Rahul Shukla, Phong Loi, Ken Pham, Arie Margulis, Kathy Yang, Nagesh Tamarapalli
Application of Test-View Modeling to Hierarchical ATPG. VLSI Design (2014)
Prabhat Mishra, Masahiro Fujita, Virendra Singh, Nagesh Tamarapalli, Sharad Kumar, Rajesh Mittal
Tutorial T10: Post - Silicon Validation, Debug and Diagnosis. VLSI Design (2013)
Srikanth Venkataraman, Nagesh Tamarapalli
Tutorial T3: DFM, DFT, Silicon Debug and Diagnosis - The Loop to Ensure Product Yield. VLSI Design (2012)
Srikanth Venkataraman, Nagesh Tamarapalli
DFM / DFT / SiliconDebug / Diagnosis. VLSI Design (2008)
Andreas Leininger, Ajay Khoche, Martin Fischer, Nagesh Tamarapalli, Wu-Tung Cheng, Randy Klingenberg, Wu Yang
The Next Step in Volume Scan Diagnosis: Standard Fail Data Format. ATS (2006)
Nandu Tendolkar, Dawit Belete, Bill Schwarz, Bob Podnar, Akshay Gupta, Steve Karako, Wu-Tung Cheng, Alex Babin, Kun-Han Tsai, Nagesh Tamarapalli, Greg Aldrich
Improving Transition Fault Test Pattern Quality through At-Speed Diagnosis. ITC (2006)
Martin Keim, Nagesh Tamarapalli, Huaxing Tang, Manish Sharma, Janusz Rajski, Chris Schuermyer, Brady Benware
A Rapid Yield Learning Flow Based on Production Integrated Layout-Aware Diagnosis. ITC (2006)
David Abercrombie, Bernd Koenemann, Nagesh Tamarapalli, Srikanth Venkataraman
DFM, DFT, Silicon Debug and Diagnosis - The Loop to Ensure Product Yield. VLSI Design (2006)
Yu Huang, Wu-Tung Cheng, Nagesh Tamarapalli, Janusz Rajski, Randy Klingenberg, Will Hsu, Yuan-Shih Chen
Diagnosis with Limited Failure Information. ITC (2006)
Andreas Leininger, Peter Muhmenthaler, Wu-Tung Cheng, Nagesh Tamarapalli, Wu Yang, Kun-Han Hans Tsai
Compression mode diagnosis enables high volume monitoring diagnosis flow. ITC (2005)
Nagesh Tamarapalli
Achieving higher yield through diagnosis. ITC (2005)
Wu-Tung Cheng, Kun-Han Tsai, Yu Huang, Nagesh Tamarapalli, Janusz Rajski
Compactor Independent Direct Diagnosis. Asian Test Symposium (2004)
Frank Poehl, Matthias Beck, Ralf Arnold, Peter Muhmenthaler, Nagesh Tamarapalli, Mark Kassab, Nilanjan Mukherjee, Janusz Rajski
Industrial Experience with Adoption of EDT for Low-Cost Test without Concessions. ITC (2003)
Janusz Rajski, Mark Kassab, Nilanjan Mukherjee, Nagesh Tamarapalli, Jerzy Tyszer, Jun Qian
Embedded Deterministic Test for Low-Cost Manufacturing. IEEE Des. Test Comput. 20 (5) (2003)
Xijiang Lin, Ron Press, Janusz Rajski, Paul Reuter, Thomas Rinderknecht, Bruce Swanson, Nagesh Tamarapalli
High-Frequency, At-Speed Scan Testing. IEEE Des. Test Comput. 20 (5) (2003)
Brady Benware, Chris Schuermyer, Sreenevasan Ranganathan, Robert Madge, Prabhu Krishnamurthy, Nagesh Tamarapalli, Kun-Han Tsai, Janusz Rajski
Impact of Multiple-Detect Test Patterns on Product Quality. ITC (2003)
Janusz Rajski, Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee, Rob Thompson, Kun-Han Tsai, Andre Hertwig, Nagesh Tamarapalli, Grzegorz Mrugalski, Geir Eide, Jun Qian
Embedded Deterministic Test for Low-Cost Manufacturing Test. ITC (2002)
Janusz Rajski, Nagesh Tamarapalli, Jerzy Tyszer
Automated synthesis of phase shifters for built-in self-testapplications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19 (10) (2000)
Graham Hetherington, Tony Fryars, Nagesh Tamarapalli, Mark Kassab, Abu S. M. Hassan, Janusz Rajski
Logic BIST for large industrial designs: real issues and case studies. ITC (1999)
Janusz Rajski, Nagesh Tamarapalli, Jerzy Tyszer
Automated synthesis of large phase shifters for built-in self-test. ITC (1998)
Nagesh Tamarapalli, Janusz Rajski
Constructive Multi-Phase Test Point Insertion for Scan-Based BIST. ITC (1996)