Grzegorz Mrugalski

Publication Activity (10 Years)

Years Active: 1999-2023
Publications (10 Years): 13

Top Topics

Relaxation Algorithm

Compression Ratio

Integrity Checking

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer, Bartosz Wlodarczak
X-Masking for Deterministic In-System Tests. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (11) (2023)
Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer, Bartosz Wlodarczak
DIST: Deterministic In-System Test with X-masking. ITC (2022)
Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer, Bartosz Wlodarczak
X-Masking for In-System Deterministic Test. ETS (2022)
Bartosz Kaczmarek, Grzegorz Mrugalski, Nilanjan Mukherjee, Artur Pogiel, Janusz Rajski, Lukasz Rybak, Jerzy Tyszer
LBIST for Automotive ICs With Enhanced Test Generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (7) (2022)
Wu-Tung Cheng, Sylwester Milewski, Grzegorz Mrugalski, Janusz Rajski, Maciej Trawka, Jerzy Tyszer
Autonomous Scan Patterns for Laser Voltage Imaging. IEEE Trans. Emerg. Top. Comput. 9 (2) (2021)
Yingdi Liu, Sylwester Milewski, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, Bartosz Wlodarczak
X-Tolerant Compactor maXpress for In-System Test Applications With Observation Scan. IEEE Trans. Very Large Scale Integr. Syst. 29 (8) (2021)
Bartosz Kaczmarek, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Lukasz Rybak, Jerzy Tyszer
Test Sequence-Optimized BIST for Automotive Applications. ETS (2020)
Jakub Janicki, Grzegorz Mrugalski, Artur Stelmach, Szczepan Urban
Scan Chain Diagnosis-Driven Test Response Compactor. ATS (2020)
Yingdi Liu, Sylwester Milewski, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, Bartosz Wldarczak
X-Tolerant Tunable Compactor for In-System Test. ITC (2020)
Wu-Tung Cheng, Grzegorz Mrugalski, Janusz Rajski, Maciej Trawka, Jerzy Tyszer
Scan Integrity Tests for EDT Compression. IEEE Des. Test 37 (4) (2020)
Wu-Tung Cheng, Grzegorz Mrugalski, Janusz Rajski, Maciej Trawka, Jerzy Tyszer
On Cyclic Scan Integrity Tests for EDT-based Compression. VTS (2019)
Grzegorz Mrugalski, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer, Chen Wang
Trimodal Scan-Based Test Paradigm. IEEE Trans. Very Large Scale Integr. Syst. 25 (3) (2017)
Grzegorz Mrugalski, Janusz Rajski, Lukasz Rybak, Jedrzej Solecki, Jerzy Tyszer
Star-EDT: Deterministic On-Chip Scheme Using Compressed Test Patterns. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36 (4) (2017)
Grzegorz Mrugalski, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer, Chen Wang
TestExpress - New Time-Effective Scan-Based Deterministic Test Paradigm. ATS (2015)
Michal Filipek, Grzegorz Mrugalski, Nilanjan Mukherjee, Benoit Nadeau-Dostie, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer
Low-Power Programmable PRPG With Test Compression Capabilities. IEEE Trans. Very Large Scale Integr. Syst. 23 (6) (2015)
Grzegorz Mrugalski, Janusz Rajski, Lukasz Rybak, Jedrzej Solecki, Jerzy Tyszer
A deterministic BIST scheme based on EDT-compressed test patterns. ITC (2015)
Wu-Tung Cheng, Yan Dong, Grady Giles, Yu Huang, Jakub Janicki, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
Scan Test Bandwidth Management for Ultralarge-Scale System-on-Chip Architectures. IEEE Trans. Very Large Scale Integr. Syst. 23 (6) (2015)
Maciej Trawka, Grzegorz Mrugalski, Nilanjan Mukherjee, Artur Pogiel, Janusz Rajski, Jakub Janicki, Jerzy Tyszer
High-Speed Serial Embedded Deterministic Test for System-on-Chip Designs. ATS (2014)
Jakub Janicki, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
Erratum to "Test Time Reduction in EDT Bandwidth Management for SoC Designs". IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33 (1) (2014)
Marcin Gebala, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
On Using Implied Values in EDT-based Test Compression. DAC (2014)
Sylwester Milewski, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer
Low Power Test Compression with Programmable Broadcast-Based Control. ATS (2014)
Jakub Janicki, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
Test Time Reduction in EDT Bandwidth Management for SoC Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32 (11) (2013)
Jerzy Tyszer, Michal Filipek, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski
New test compression scheme based on low power BIST. ETS (2013)
Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
On Deploying Scan Chains for Data Storage in Test Compression Environment. IEEE Des. Test 30 (1) (2013)
Jedrzej Solecki, Jerzy Tyszer, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski
Low power programmable PRPG with enhanced fault coverage gradient. ITC (2012)
Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Benoit Nadeau-Dostie
Test generator with preselected toggling for low power built-in self-test. VTS (2012)
Jakub Janicki, Jerzy Tyszer, Grzegorz Mrugalski, Janusz Rajski
Bandwidth-aware test compression logic for SoC designs. ETS (2012)
Jakub Janicki, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
EDT Bandwidth Management in SoC Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31 (12) (2012)
Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
Reduced ATE Interface for High Test Data Compression. ETS (2011)
Nilanjan Mukherjee, Janusz Rajski, Grzegorz Mrugalski, Artur Pogiel, Jerzy Tyszer
Ring Generator: An Ultimate Linear Feedback Shift Register. Computer 44 (6) (2011)
Jakub Janicki, Jerzy Tyszer, Avijit Dutta, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski
EDT channel bandwidth management in SoC designs with pattern-independent test access mechanism. ITC (2011)
Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Przemyslaw Szczerbicki, Jerzy Tyszer
Deterministic Clustering of Incompatible Test Cubes for Higher Power-Aware EDT Compression. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30 (8) (2011)
Michal Filipek, Yoshiaki Fukui, Hiroyuki Iwata, Grzegorz Mrugalski, Janusz Rajski, Masahiro Takakura, Jerzy Tyszer
Low Power Decompressor and PRPG with Constant Value Broadcast. Asian Test Symposium (2011)
Brady Benware, Grzegorz Mrugalski, Artur Pogiel, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer
Diagnosis of Failing Scan Cells through Orthogonal Response Compaction. ETS (2011)
Brady Benware, Grzegorz Mrugalski, Artur Pogiel, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer
Fault Diagnosis with Orthogonal Compactors in Scan-Based Designs. J. Electron. Test. 27 (5) (2011)
Grzegorz Mrugalski, Artur Pogiel, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, Pawel Urbanek
Fault Diagnosis in Memory BIST Environment with Non-march Tests. Asian Test Symposium (2011)
Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jakub Janicki, Jerzy Tyszer
Dynamic channel allocation for higher EDT compression in SoC designs. ITC (2010)
Brady Benware, Grzegorz Mrugalski, Artur Pogiel, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer
Diagnosis of failing scan cells through orthogonal response compaction. ETS (2010)
Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
On Compaction Utilizing Inter and Intra-Correlation of Unknown States. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (1) (2010)
Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Przemyslaw Szczerbicki, Jerzy Tyszer
Low power compression of incompatible test cubes. ITC (2010)
Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Dariusz Czysz, Jerzy Tyszer
Highly X-Tolerant Selective Compaction of Test Responses. VTS (2009)
Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Dariusz Czysz, Jerzy Tyszer
Compression based on deterministic vector clustering of incompatible test cubes. ITC (2009)
Dariusz Czysz, Mark Kassab, Xijiang Lin, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer
Low-Power Scan Operation in Test Compression Environment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28 (11) (2009)
Dariusz Czysz, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer
Low-Power Test Data Application in EDT Environment Through Decompressor Freeze. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27 (7) (2008)
Dariusz Czysz, Mark Kassab, Xijiang Lin, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer
Low Power Scan Shift and Capture in the EDT Environment. ITC (2008)
Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Wu-Tung Cheng, Nilanjan Mukherjee, Mark Kassab
X-Press: Two-Stage X-Tolerant Compactor With Programmable Selector. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27 (1) (2008)
Grzegorz Mrugalski, Janusz Rajski, Chen Wang, Artur Pogiel, Jerzy Tyszer
Isolation of Failing Scan Cells through Convolutional Test Response Compaction. J. Electron. Test. 23 (1) (2007)
Jerzy Tyszer, Janusz Rajski, Grzegorz Mrugalski, Nilanjan Mukherjee, Mark Kassab, Wu-Tung Cheng, Manish Sharma, Liyang Lai
X-Tolerant Compactor with On-Chip Registration and Signature-Based Diagnosis. IEEE Des. Test Comput. 24 (5) (2007)
Grzegorz Mrugalski, Janusz Rajski, Dariusz Czysz, Jerzy Tyszer
New Test Data Decompressor for Low Power Applications. DAC (2007)
Grzegorz Mrugalski, Artur Pogiel, Janusz Rajski, Jerzy Tyszer
Fault Diagnosis With Convolutional Compactors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (8) (2007)
Dariusz Czysz, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer
Low Power Embedded Deterministic Test. VTS (2007)
Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Wu-Tung Cheng, Nilanjan Mukherjee, Mark Kassab
X-Press Compactor for 1000x Reduction of Test Data. ITC (2006)
Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
High Performance Dense Ring Generators. IEEE Trans. Computers 55 (1) (2006)
Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer
Test response compactor with programmable selector. DAC (2006)
Grzegorz Mrugalski, Artur Pogiel, Janusz Rajski, Jerzy Tyszer
Diagnosis with convolutional compactors in presence of unknown states. ITC (2005)
Grzegorz Mrugalski, Artur Pogiel, Janusz Rajski, Jerzy Tyszer, Chen Wang
Convolutional compaction-driven diagnosis of scan failures. ETS (2005)
Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
Planar High Performance Ring Generators. VTS (2004)
Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer
Ring generators - new devices for embedded test applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23 (9) (2004)
Grzegorz Mrugalski, Chen Wang, Artur Pogiel, Jerzy Tyszer, Janusz Rajski
Fault Diagnosis in Designs with Convolutional Compactors. ITC (2004)
Grzegorz Mrugalski, Jerzy Tyszer, Janusz Rajski
2D Test Sequence Generators. IEEE Des. Test Comput. 20 (1) (2003)
Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer
High Speed Ring Generators and Compactors of Test Data. VTS (2003)
Janusz Rajski, Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee, Rob Thompson, Kun-Han Tsai, Andre Hertwig, Nagesh Tamarapalli, Grzegorz Mrugalski, Geir Eide, Jun Qian
Embedded Deterministic Test for Low-Cost Manufacturing Test. ITC (2002)
Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer
Cellular automata-based test pattern generators with phase shifters. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19 (8) (2000)
Grzegorz Mrugalski, Jerzy Tyszer, Janusz Rajski
Linear Independence as Evaluation Criterion for Two-Dimensional Test Pattern Generators. VTS (2000)
Janusz Rajski, Grzegorz Mrugalski, Jerzy Tyszer
Comparative Study of CA-based PRPGs and LFSRs with Phase Shifters. VTS (1999)
Grzegorz Mrugalski, Jerzy Tyszer, Janusz Rajski
Synthesis of pattern generators based on cellular automata with phase shifters. ITC (1999)