Benoit Nadeau-Dostie

Publication Activity (10 Years)

Years Active: 1989-2024
Publications (10 Years): 9

Top Topics

Design Methodologies

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Luc Romain, Paul-Patrick Nordmann, Benoit Nadeau-Dostie, Lori Schramm, Martin Keim
Combining Built-In Redundancy Analysis with ECC for Memory Testing. ETS (2024)
Cyrille Dray, Khushal Gelda, Benoit Nadeau-Dostie, Wei Zou, Luc Romain, Jongsin Yun, Harshitha Kodali, Lori Schramm, Martin Keim
Transitioning eMRAM from Pilot Project to Volume Production. ITC (2023)
Wei Zou, Benoit Nadeau-Dostie
Configurable BISR Chain For Fast Repair Data Loading. ITC (2022)
Jongsin Yun, Benoit Nadeau-Dostie, Martin Keim, Lori Schramm, Cyrille Dray, El Mehdi Boujamaa, Khushal Gelda
MBIST Supported Multi Step Trim for Reliable eMRAM Sensing. ITC (2020)
Benoit Nadeau-Dostie, Luc Romain
Memory repair logic sharing techniques and their impact on yield. ITC (2020)
Jongsin Yun, Benoit Nadeau-Dostie, Martin Keim, Cyrille Dray, El Mehdi Boujamaa
MBIST Support for Reliable eMRAM Sensing. ETS (2020)
Venkat Yellapragada, Suresh Raman, Banadappa Shivaray, Luc Romain, Benoit Nadeau-Dostie, Martin Keim, Jean-Francois Cote, Albert Au, Giri Podichetty, Ashok Anbalan
Implementing Design-for-Test Within a Tile-Based Design Methodology - Challenges and Solutions. ITC-Asia (2018)
Jais Abraham, Uttam Garg, Glenn Colón-Bonet, Ramesh Sharma, Chennian Di, Benoit Nadeau-Dostie, Etienne Racine, Martin Keim
Adapting an industrial memory BIST solution for testing CAMs. ITC-Asia (2017)
Michal Filipek, Grzegorz Mrugalski, Nilanjan Mukherjee, Benoit Nadeau-Dostie, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer
Low-Power Programmable PRPG With Test Compression Capabilities. IEEE Trans. Very Large Scale Integr. Syst. 23 (6) (2015)
Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Benoit Nadeau-Dostie
Test generator with preselected toggling for low power built-in self-test. VTS (2012)
Joon-Sung Yang, Nur A. Touba, Benoit Nadeau-Dostie
Test Point Insertion with Control Points Driven by Existing Functional Flip-Flops. IEEE Trans. Computers 61 (10) (2012)
Xijiang Lin, Elham K. Moghaddam, Nilanjan Mukherjee, Benoit Nadeau-Dostie, Janusz Rajski, Jerzy Tyszer
Power Aware Embedded Test. Asian Test Symposium (2011)
Joon-Sung Yang, Benoit Nadeau-Dostie, Nur A. Touba
Test point insertion using functional flip-flops to drive control points. ITC (2009)
Benoit Nadeau-Dostie, Saman Adham, Russell Abbott
Improved Core Isolation and Access for Hierarchical Embedded Test. IEEE Des. Test Comput. 26 (1) (2009)
Joon-Sung Yang, Benoit Nadeau-Dostie, Nur A. Touba
Reducing Test Point Area for BIST through Greater Use of Functional Flip-Flops to Drive Control Points. DFT (2009)
Benoit Nadeau-Dostie, Kiyoshi Takeshita, Jean-Francois Cote
Power-Aware At-Speed Scan Test Methodology for Circuits with Synchronous Clocks. ITC (2008)
Bruce Cory, Rohit Kapur, Mick Tegethoff, Mark Kassab, Brion L. Keller, Kee Sup Kim, Dwayne Burek, Steven F. Oakland, Benoit Nadeau-Dostie
OCI: Open Compression Interface. ITC (2006)
Saman Adham, Benoit Nadeau-Dostie
A BIST Algorithm for Bit/Group Write Enable Faults in SRAMs. MTDT (2004)
Stephen K. Sunter, Benoit Nadeau-Dostie
Complete, Contactless I/O Testing - Reaching the Boundary in Minimizing Digital IC Testing Cost. ITC (2002)
Benoit Nadeau-Dostie, Jean-Francois Cote, Harry Hulvershorn, Stephen Pateras
An embedded technique for at-speed interconnect testing. ITC (1999)
Samir Boubezari, Eduard Cerny, Bozena Kaminska, Benoit Nadeau-Dostie
Testability analysis and test-point insertion in RTL VHDL specifications for scan-based BIST. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18 (9) (1999)
Bernd Könemann, Ben Bennetts, Najmi T. Jarwala, Benoit Nadeau-Dostie
Built-In Self-Test: Assuring System Integrity. Computer 29 (11) (1996)
Benoit Nadeau-Dostie, Harry Hulvershorn, Saman Adham
A New Hardware Fault Insertion Scheme for System Diagnostics Verification. ITC (1995)
Benoit Nadeau-Dostie, Dwayne Burek, Abu S. M. Hassan
ScanBist: A Multifrequency Scan-Based BIST Method. IEEE Des. Test Comput. 11 (1) (1994)
Michael M. Y. Hui, Benoit Nadeau-Dostie
Scan testing of latch arrays. VTS (1992)
Benoit Nadeau-Dostie, Dwayne Burek, Abu S. M. Hassan
ScanBIST: A Multi-frequency Scan-based BIST Method. ITC (1992)
Abu S. M. Hassan, Vinod K. Agarwal, Benoit Nadeau-Dostie, Janusz Rajski
BIST of PCB interconnects using boundary-scan architecture. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11 (10) (1992)
Benoit Nadeau-Dostie, Allan Silburt, Vinod K. Agarwal
Serial Interfacing for Embedded-Memory Testing. IEEE Des. Test Comput. 7 (2) (1990)
Fidel Muradali, Vinod K. Agarwal, Benoit Nadeau-Dostie
A new procedure for weighted random built-in self-test. ITC (1990)
Abu S. M. Hassan, Vinod K. Agarwal, Janusz Rajski, Benoit Nadeau-Dostie
Testing of Glue Logic Interconnects Using Boundary Scan Architecture. ITC (1989)