Stephen K. Sunter

Publication Activity (10 Years)

Years Active: 1995-2016
Publications (10 Years): 1

Top Topics

Solution Quality

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

IEEE Des. Test Comput.

Publications

Stephen K. Sunter, Jean-Francois Cote, Jeff Rearick
Streaming Access to ADCs and DACs for Mixed-Signal ATPG. IEEE Des. Test 33 (6) (2016)
Stephen K. Sunter, Jean-Francois Cote, Jeff Rearick
Streaming fast access to ADCs and DACs for mixed-signal ATPG. ITC (2015)
Amitava Majumdar, Suriya Natarajan, Stephen K. Sunter, Prashant Goteti, Ke Huang
Innovative practices session 4C: Disruptive solutions in the non-digital world. VTS (2014)
Stephen K. Sunter, Steve Comen, Paul Berndt, Ram Rajamani
Innovative practices session 7C: Reduced pin-count testing - How low can we go? VTS (2014)
Li-Ren Huang, Shi-Yu Huang, Stephen K. Sunter, Kun-Han Tsai, Wu-Tung Cheng
Oscillation-Based Prebond TSV Test. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32 (9) (2013)
Yu-Hsiang Lin, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng, Stephen K. Sunter, Yung-Fa Chou, Ding-Ming Kwai
Parametric Delay Test of Post-Bond Through-Silicon Vias in 3-D ICs via Variable Output Thresholding Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32 (5) (2013)
Li-Ren Huang, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng, Stephen K. Sunter
Mid-bond Interposer Wire Test. Asian Test Symposium (2013)
Yu-Hsiang Lin, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng, Stephen K. Sunter
A unified method for parametric fault characterization of post-bond TSVs. ITC (2012)
Stephen K. Sunter, Aubin Roy
Contactless Test of IC Pads, Pins, and TSVs via Standard Boundary Scan. IEEE Des. Test Comput. 29 (5) (2012)
Shi-Yu Huang, Yu-Hsiang Lin, Kun-Han Tsai, Wu-Tung Cheng, Stephen K. Sunter, Yung-Fa Chou, Ding-Ming Kwai
Small delay testing for TSVs in 3-D ICs. DAC (2012)
Stephen K. Sunter, Aubin Roy
Adaptive parametric BIST of high-speed parallel I/Os via standard boundary scan. ITC (2011)
Stephen K. Sunter, Aubin Roy
A Mixed-Signal Test Bus and Analog BIST with 'Unlimited' Time and Voltage Resolution. ETS (2011)
Rakesh Kinger, Swetha Narasimhawsamy, Stephen K. Sunter
Experiences with parametric BIST for production testing PLLs with picosecond precision. ITC (2010)
Stephen K. Sunter, Matthias Tilmann
BIST of I/O circuit parameters via standard boundary scan. ITC (2010)
Stephen K. Sunter, Aubin Roy
Noise-Insensitive Digital BIST for any PLL or DLL. J. Electron. Test. 24 (5) (2008)
Stephen K. Sunter, Aubin Roy
A selt-testing BOST for high-frequency PLLs, DLLs, and SerDes. ITC (2007)
Stephen K. Sunter, Aubin Roy
Purely Digital BIST for Any PLL or DLL. ETS (2007)
Stephen K. Sunter, Aubin Roy
Testing SerDes beyond 4 Gbps - changing priorities. CICC (2007)
Stephen K. Sunter, Aubin Roy
Structural Tests for Jitter Tolerance in SerDes Receivers. ITC (2006)
Bozena Kaminska, Stephen K. Sunter, Salvador Mir
Analog and mixed signal test techniques for SOC development. Microelectron. J. 36 (12) (2005)
Stephen K. Sunter
Correct by construction is guaranteed to fail. ITC (2005)
Stephen K. Sunter, Aubin Roy
Structural tests for jitter tolerance in SerDes receivers. ITC (2005)
Stephen K. Sunter, Aubin Roy, Jean-Francois Cote
An Automated, Complete, Structural Test Solution for SERDES. ITC (2004)
Stephen K. Sunter, Adam Osseiran, Adam Cron, Neil G. Jacobson, Dave Bonnett, Bill Eklow, Carl Barnhart, Ben Bennetts
Status of IEEE Testability Standards 1149.4, 1532 and 1149.6. DATE (2004)
Stephen K. Sunter, Aubin Roy
On-Chip Digital Jitter Measurement, from Megahertz to Gigahertz. IEEE Des. Test Comput. 21 (4) (2004)
Stephen K. Sunter
Testing High Frequency ADCs and DACs with a Low Frequency Analog Bus. ITC (2003)
Aubin Roy, Stephen K. Sunter, Alessandra Fudoli, Davide Appello
High Accuracy Stimulus Generation for A/D Converter BIST. ITC (2002)
Stephen K. Sunter, Benoit Nadeau-Dostie
Complete, Contactless I/O Testing - Reaching the Boundary in Minimizing Digital IC Testing Cost. ITC (2002)
Stephen K. Sunter
IC Mixed-Signal BIST: Separating Facts from Fiction. ITC (2002)
Stephen K. Sunter, Charles McDonald, Givargis Danialy
Contactless digital testing of IC pin leakage currents. ITC (2001)
Stephen K. Sunter, Ken Filliter, Joe Woo, Pat McHugh
A general purpose 1149.4 IC with HF analog test capabilities. ITC (2001)
Thomas W. Williams, Stephen K. Sunter
How Should Fault Coverage Be Defined? VTS (2000)
Stephen K. Sunter, Aubin Roy
BIST for phase-locked loops in digital applications. ITC (1999)
Stephen K. Sunter
Analog, digital, and mixed-signal people. IEEE Des. Test Comput. 16 (3) (1999)
Stephen K. Sunter, Naveena Nagi
Test Metrics for Analog Parametric Faults. VTS (1999)
Stephen K. Sunter
BIST vs. ATE: need a different vehicle? ITC (1998)
Stephen K. Sunter, Naveena Nagi
A Simplified Polynomial-Fitting Algorithm for DAC and ADC BIST. ITC (1997)
Stephen K. Sunter
P1149.4-Problem or Solution for Mixed-Signal IC Design? ITC (1997)
Karim Arabi, Bozena Kaminska, Stephen K. Sunter
Design for testability of integrated operational amplifiers using oscillation-test strategy. ICCD (1996)
Stephen K. Sunter
A low cost 100 MHz analog test bus. VTS (1995)
Stephen K. Sunter
The P1149.4 Mixed Signal Test Bus: Costs and Benefits. ITC (1995)