Thomas W. Williams

Publication Activity (10 Years)

Years Active: 1972-2008
Publications (10 Years): 0

Publications

Srinivasulu Alampally, Jais Abraham, Rubin A. Parekhji, Rohit Kapur, Thomas W. Williams
Evaluation of Entropy Driven Compression Bounds on Industrial Designs. ATS (2008)
Thomas W. Williams
EDA to the Rescue of the Silicon Roadmap. ISMVL (2008)
J. S. Hobbs, Thomas W. Williams
Reaching the limits of low power design. ASP-DAC (2008)
Thomas W. Williams
The Future Is Low Power and Test. ETS (2008)
Rohit Kapur, Subhasish Mitra, Thomas W. Williams
Historical Perspective on Scan Compression. IEEE Des. Test Comput. 25 (2) (2008)
Thomas W. Williams
EDA to the Rescue of the Silicon Roadmap. ISQED (2007)
Rohit Kapur, Jindrich Zejda, Thomas W. Williams
Fundamentals of timing information for test: How simple can we get? ITC (2007)
Maria Gkatziani, Rohit Kapur, Qing Su, Ben Mathew, Roberto Mattiuzzo, Laura Tarantini, Cy Hay, Salvatore Talluto, Thomas W. Williams
Accurately Determining Bridging Defects from Layout. DDECS (2007)
Rohit Kapur, T. Finklea, Felix Ng, Anshuman Chandra, Sanjay Ramnath, Peter Wohl, Thomas W. Williams, Ashok Anbalan, Sandeep S. Kulkarni, Tammy Fernandes, Pramod Notiyath, Rajesh Uppuluri
DFT MAX and Power. J. Low Power Electron. 3 (2) (2007)
Peter Wohl, John A. Waicukauski, Rohit Kapur, Sanjay Ramnath, Emil Gizdarski, Thomas W. Williams, P. Jaini
Minimizing the Impact of Scan Compression. VTS (2007)
Thomas W. Williams
TTTC recognizes test visionary's lifetime contribution. IEEE Des. Test Comput. 22 (3) (2005)
Thomas W. Williams
Design for Testability: The Path to Deep Submicron. Asian Test Symposium (2005)
Peter Wohl, John A. Waicukauski, Sanjay Patel, Francisco DaSilva, Thomas W. Williams, Rohit Kapur
Efficient compression of deterministic patterns into multiple PRPG seeds. ITC (2005)
Nodari Sitchinava, Samitha Samaranayake, Rohit Kapur, Emil Gizdarski, Frederic Neuveux, Thomas W. Williams
Changing the Scan Enable during Shift. VTS (2004)
Li-C. Wang, Angela Krstic, Leonard Lee, Kwang-Ting Cheng, M. Ray Mercer, Thomas W. Williams, Magdy S. Abadir
Using Logic Models To Predict The Detection Behavior Of Statistical Timing Defects. ITC (2003)
Samitha Samaranayake, Emil Gizdarski, Nodari Sitchinava, Frederic Neuveux, Rohit Kapur, Thomas W. Williams
A Reconfigurable Shared Scan-in Architecture. VTS (2003)
Nahmsuk Oh, Rohit Kapur, Thomas W. Williams, Jim Sproch
Test Pattern Compression Using Prelude Vectors in Fan-Out Scan Chain with Feedback Architecture. DATE (2003)
Nahmsuk Oh, Rohit Kapur, Thomas W. Williams
Fast seed computation for reseeding shift register in test pattern compression. ICCAD (2002)
Jing-Jia Liou, Li-C. Wang, Kwang-Ting Cheng, Jennifer Dworak, M. Ray Mercer, Rohit Kapur, Thomas W. Williams
Enhancing test efficiency for delay fault testing using multiple-clocked schemes. DAC (2002)
Samitha Samaranayake, Nodari Sitchinava, Rohit Kapur, Minesh B. Amin, Thomas W. Williams
Dynamic Scan: Driving Down the Cost of Test. Computer 35 (10) (2002)
Jing-Jia Liou, Li-C. Wang, Kwang-Ting Cheng, Jennifer Dworak, M. Ray Mercer, Rohit Kapur, Thomas W. Williams
Analysis of Delay Test Effectiveness with a Multiple-Clock Scheme. ITC (2002)
Rohit Kapur, Thomas W. Williams, M. Ray Mercer
Directed-Binary Search in Logic BIST Diagnostics. DATE (2002)
Rohit Kapur, Thomas W. Williams
Manufacturing Test of SoCs. Asian Test Symposium (2002)
Peter Wohl, John A. Waicukauski, Thomas W. Williams
Design of compactors for signature-analyzers in built-in self-test. ITC (2001)
Ajay Khoche, Rohit Kapur, David Armstrong, Thomas W. Williams, Mick Tegethoff, Jochen Rivoir
A new methodology for improved tester utilization. ITC (2001)
Rohit Kapur, Thomas W. Williams
Tester retargetable patterns. ITC (2001)
Rohit Kapur, R. Chandramouli, Thomas W. Williams
Strategies for Low-Cost Test. IEEE Des. Test Comput. 18 (6) (2001)
Farhad Hayat, Thomas W. Williams, Rohit Kapur, D. Hsu
DFT closure. Asian Test Symposium (2000)
Rohit Kapur, Cy Hay, Thomas W. Williams
The Mutating Metric for Benchmarking Test. IEEE Des. Test Comput. 17 (3) (2000)
Thomas W. Williams, Stephen K. Sunter
How Should Fault Coverage Be Defined? VTS (2000)
Thomas W. Williams, Rohit Kapur
Design for Testability in Nanometer Technologies; Searching for Quality. ISQED (2000)
Don MacMillen, Raul Camposano, Dwight D. Hill, Thomas W. Williams
An industrial view of electronic design automation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19 (12) (2000)
Thomas W. Williams
Testing in Nanometer Technologies. DATE (1999)
Rohit Kapur, Thomas W. Williams
Tough Challenges as Design and Test Go Nanometer - Guest Editors' Introduction. Computer 32 (11) (1999)
Thomas W. Williams
IEEE-USA and the Issue of Member Choice. Computer 32 (2) (1999)
Thomas W. Williams
The New Frontier for Testing: Nano Meter Technologies. Asian Test Symposium (1998)
Thomas W. Williams, Robert H. Dennard, Rohit Kapur, M. Ray Mercer, Wojciech Maly
Test: Sensitivity Analysis of Scaling. ITC (1996)
Li-C. Wang, M. Ray Mercer, Thomas W. Williams
A Better ATPG Algorithm and Its Design Principles. ICCD (1996)
Thomas W. Williams, Rohit Kapur, M. Ray Mercer, Robert H. Dennard, Wojciech Maly
Iddq Testing for High Performance CMOS - The Next Ten Years. ED&TC (1996)
José T. de Sousa, Fernando M. Gonçalves, João Paulo Teixeira, Cristoforo Marzocca, Francesco Corsi, Thomas W. Williams
Defect level evaluation in an IC design environment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15 (10) (1996)
Rohit Kapur, Srinivas Patil, Thomas J. Snethen, Thomas W. Williams
A weighted random pattern test generation system. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15 (8) (1996)
Li-C. Wang, M. Ray Mercer, Thomas W. Williams
Using Target Faults To Detect Non-Tartget Defects. ITC (1996)
Li-C. Wang, M. Ray Mercer, Sophia W. Kao, Thomas W. Williams
On the decline of testing efficiency as fault coverage approaches 100%. VTS (1995)
Li-C. Wang, M. Ray Mercer, Thomas W. Williams
On Efficiently and Reliably Achieving Low Defective Part Levels. ITC (1995)
Li-C. Wang, M. Ray Mercer, Thomas W. Williams
Enhanced testing performance via unbiased test sets. ED&TC (1995)
Rohit Kapur, Srinivas Patil, Thomas J. Snethen, Thomas W. Williams
Design of an Efficient Weighted-Random-Pattern Generation System. ITC (1994)
José T. de Sousa, Fernando M. Gonçalves, João Paulo Teixeira, Thomas W. Williams
Fault Modeling and Defect Level Projections in Digital ICs. EDAC-ETC-EUROASIC (1994)
Jaehong Park, Mark Naivar, Rohit Kapur, M. Ray Mercer, Thomas W. Williams
Limitations in predicting defect level based on stuck-at fault coverage. VTS (1994)
Thomas W. Williams
Design for Testability: Today and in the Future. ICCD (1993)
Eun Sei Park, M. Ray Mercer, Thomas W. Williams
The Total Delay Fault Model and Statistical Delay Fault Coverage. IEEE Trans. Computers 41 (6) (1992)
Eun Sei Park, Bill Underwood, Thomas W. Williams, M. Ray Mercer
Delay Testing Quality in Timing-Optimized Designs. ITC (1991)
Thomas W. Williams, Bill Underwood, M. Ray Mercer
The Interdependence Between Delay-Optimization of Synthesized Networks and Testing. DAC (1991)
Kenneth D. Wagner, Thomas W. Williams
Enhancing Board Functional Self-Test by Concurrent Sampling. ITC (1991)
Thomas W. Williams
Future Trends in the Testing. IFIP Congress (1989)
Eun Sei Park, M. Ray Mercer, Thomas W. Williams
A statistical model for delay-fault testing. IEEE Des. Test 6 (1) (1989)
Kenneth D. Wagner, Thomas W. Williams
Design for Testability of Mixed Signal Integrated Circuits. ITC (1988)
Eun Sei Park, Thomas W. Williams, M. Ray Mercer
Statistical Delay Fault Coverage and Defect Level for Delay Faults. ITC (1988)
Thomas W. Williams
Design of testable logic circuits. Proc. IEEE 74 (3) (1986)
Thomas W. Williams
Test Length in a Self-Testing Environment. IEEE Des. Test 2 (2) (1985)
Thomas W. Williams
VLSI Testing. Computer 17 (10) (1984)
Eugen I. Muehldorf, Thomas W. Williams
Analysis of the Switching Behavior of Combinatorial Logic Networks. ITC (1982)
Thomas W. Williams
Design for testability. DAC (1982)
Thomas W. Williams, Kenneth P. Parker
Design for Testability - A Survey. IEEE Trans. Computers 31 (1) (1982)
Thomas W. Williams, Kenneth P. Parker
Testing Logic Networks and Designing for Testability. Computer 12 (10) (1979)
Edward B. Eichelberger, Thomas W. Williams
A logic design structure for LSI testability. DAC (1977)
Daniel J. Krause, John W. Steadman, Thomas W. Williams
Effect of Record Length on Noise-Induced Error in the Cross Correlation Estimate. IEEE Trans. Syst. Man Cybern. 2 (2) (1972)