Angela Krstic

Publication Activity (10 Years)

Years Active: 1995-2004
Publications (10 Years): 0

Publications

T. M. Mak, Angela Krstic, Kwang-Ting (Tim) Cheng, Li-C. Wang
New Challenges in Delay Testing of Nanometer, Multigigahertz Designs. IEEE Des. Test Comput. 21 (3) (2004)
Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, Jing-Jia Liou, Magdy S. Abadir
Delay Defect Diagnosis Based Upon Statistical Timing Models - The First Step. DATE (2003)
Li-C. Wang, Angela Krstic, Leonard Lee, Kwang-Ting Cheng, M. Ray Mercer, Thomas W. Williams, Magdy S. Abadir
Using Logic Models To Predict The Detection Behavior Of Statistical Timing Defects. ITC (2003)
Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, Jing-Jia Liou, T. M. Mak
Enhancing diagnosis resolution for delay defects based upon statistical timing and statistical fault models. DAC (2003)
Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, Jing-Jia Liou
Diagnosis of Delay Defects Using Statistical Timing Models. VTS (2003)
Xiaoliang Bai, Sujit Dey, Angela Krstic
HyAC: A Hybrid Structural SAT Based ATPG for Crosstalk. ITC (2003)
Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, T. M. Mak
Diagnosis-Based Post-Silicon Timing Validation Using Statistical Tools and Methodologies. ITC (2003)
Jing-Jia Liou, Angela Krstic, Yi-Min Jiang, Kwang-Ting Cheng
Modeling, testing, and analysis for delay defects and noise effects in deep submicron devices. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22 (6) (2003)
Jing-Jia Liou, Li-C. Wang, Angela Krstic, Kwang-Ting Cheng
Experience in critical path selection for deep sub-micron delay test and timing validation. ASP-DAC (2003)
Jing-Jia Liou, Li-C. Wang, Angela Krstic, Kwang-Ting (Tim) Cheng
Critical Path Selection for Deep Sub-Micron Delay Test and Timing Validation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2003)
Angela Krstic, Jing-Jia Liou, Kwang-Ting Cheng, Li-C. Wang
On Structural vs. Functional Testing for Delay Faults. ISQED (2003)
Angela Krstic, Wei-Cheng Lai, Kwang-Ting Cheng, Li Chen, Sujit Dey
Embedded Software-Based Self-Test for Programmable Core-Based Designs. IEEE Des. Test Comput. 19 (4) (2002)
Angela Krstic, Wei-Cheng Lai, Kwang-Ting Cheng, Li Chen, Sujit Dey
Embedded software-based self-testing for SoC design. DAC (2002)
Jing-Jia Liou, Angela Krstic, Li-C. Wang, Kwang-Ting Cheng
False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation. DAC (2002)
Jing-Jia Liou, Kwang-Ting Cheng, Sandip Kundu, Angela Krstic
Fast Statistical Timing Analysis By Probabilistic Event Propagation. DAC (2001)
Angela Krstic, Jing-Jia Liou, Yi-Min Jiang, Kwang-Ting Cheng
Delay testing considering crosstalk-induced effects. ITC (2001)
Angela Krstic, Yi-Min Jiang, Kwang-Ting Cheng
Pattern generation for delay testing and dynamic timing analysisconsidering power-supply noise effects. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20 (3) (2001)
Jing-Jia Liou, Angela Krstic, Yi-Min Jiang, Kwang-Ting Cheng
Path Selection and Pattern Generation for Dynamic Timing Analysis Considering Power Supply Noise Effects. ICCAD (2000)
Wei-Cheng Lai, Angela Krstic, Kwang-Ting Cheng
Test program synthesis for path delay faults in microprocessor cores. ITC (2000)
Yi-Min Jiang, Angela Krstic, Kwang-Ting Cheng
Estimation for maximum instantaneous current through supply lines for CMOS circuits. IEEE Trans. Very Large Scale Integr. Syst. 8 (1) (2000)
Wei-Cheng Lai, Angela Krstic, Kwang-Ting (Tim) Cheng
Functionally Testable Path Delay Faults on a Microprocessor. IEEE Des. Test Comput. 17 (4) (2000)
Jing-Jia Liou, Angela Krstic, Kwang-Ting Cheng, Deb Aditya Mukherjee, Sandip Kundu
Performance sensitivity analysis using statistical method and its applications to delay. ASP-DAC (2000)
Yi-Min Jiang, Angela Krstic, Kwang-Ting Cheng
Dynamic Timing Analysis Considering Power Supply Noise Effects. ISQED (2000)
Wei-Cheng Lai, Angela Krstic, Kwang-Ting Cheng
On Testing the Path Delay Faults of a Microprocessor Using its Instruction Set. VTS (2000)
Angela Krstic, Srimat T. Chakradhar, Kwang-Ting Cheng
Testable Path Delay Fault Cover for Sequential Circuits. J. Inf. Sci. Eng. 16 (5) (2000)
Angela Krstic, Kwang-Ting (Tim) Cheng, Srimat T. Chakradhar
Testing High Speed VLSI Devices Using Slower Testers. VTS (1999)
Kwang-Ting Cheng, Angela Krstic
Current Directions in Automatic Test-Pattern Generation. Computer 32 (11) (1999)
Yi-Min Jiang, Angela Krstic, Kwang-Ting Cheng
Delay testing considering power supply noise effects. ITC (1999)
Angela Krstic, Kwang-Ting Cheng, Srimat T. Chakradhar
Primitive delay faults: identification, testing, and design for testability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18 (6) (1999)
Yi-Min Jiang, Angela Krstic, Kwang-Ting Cheng, Malgorzata Marek-Sadowska
Post-Layout Logic Restructuring for Performance Optimization. DAC (1997)
Angela Krstic, Kwang-Ting Cheng, Srimat T. Chakradhar
Design for Primitive Delay Fault Testability. ITC (1997)
Angela Krstic, Kwang-Ting Cheng
Vector Generation for Maximum Instantaneous Current Through Supply Lines for CMOS Circuits. DAC (1997)
Angela Krstic, Kwang-Ting Cheng
Resynthesis of Combinational Circuits for Path Count Reduction and for Path Delay Fault Testability. J. Electron. Test. 11 (1) (1997)
Angela Krstic, Kwang-Ting Cheng, Srimat T. Chakradhar
Testable path delay fault cover for sequential circuits. EURO-DAC (1996)
Angela Krstic, Kwang-Ting Cheng, Srimat T. Chakradhar
Identification and Test Generation for Primitive Faults. ITC (1996)
Kwang-Ting Cheng, Angela Krstic, Hsi-Chuan Chen
Generation of High Quality Tests for Robustly Untestable Path Delay Faults. IEEE Trans. Computers 45 (12) (1996)
Angela Krstic, Kwang-Ting Cheng
Resynthesis of Combinational Circuts for Path Count Reduction and for Path Delay Fault Testability. ED&TC (1996)
Angela Krstic, Kwang-Ting Cheng
Generation of high quality tests for functional sensitizable paths. VTS (1995)