Yi-Min Jiang

Publication Activity (10 Years)

Years Active: 1992-2022
Publications (10 Years): 1

Top Topics

Traffic Congestion

Machine Learning

Multiple Models

Top Venues

Theor. Comput. Sci.

Publications

Xiang Gao, Yi-Min Jiang, Lixin Shao, Pedja Raspopovic, Menno E. Verbeek, Manish Sharma, Vineet Rashingkar, Amit Jalota
Congestion and Timing Aware Macro Placement Using Machine Learning Predictions from Different Data Sources: Cross-design Model Applicability and the Discerning Ensemble. ISPD (2022)
Yi-Hao Zhang, Yue-Hong Shen, Min Dong, Yi-Min Jiang
A method of batching conflict routings in shuffle-exchange networks. Theor. Comput. Sci. 522 (2014)
Kaijian Shi, Zhian Lin, Yi-Min Jiang, Lin Yuan
Simultaneous Sleep Transistor Insertion and Power Network Synthesis for Industrial Power Gating Designs. J. Comput. 3 (3) (2008)
Kaijian Shi, Zhian Lin, Yi-Min Jiang
A Power Network Synthesis Method for Industrial Power Gating Designs. ISQED (2007)
Jing-Jia Liou, Angela Krstic, Yi-Min Jiang, Kwang-Ting Cheng
Modeling, testing, and analysis for delay defects and noise effects in deep submicron devices. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22 (6) (2003)
Yi-Min Jiang, Kwang-Ting Cheng
Vector generation for power supply noise estimation and verification of deep submicron designs. IEEE Trans. Very Large Scale Integr. Syst. 9 (2) (2001)
Yi-Min Jiang, Han Young Koh, Kwang-Ting Cheng
HRM - A Hierarchical Simulator for Full-Chip Power Network Reliability Analysis. ISQED (2001)
Angela Krstic, Jing-Jia Liou, Yi-Min Jiang, Kwang-Ting Cheng
Delay testing considering crosstalk-induced effects. ITC (2001)
Angela Krstic, Yi-Min Jiang, Kwang-Ting Cheng
Pattern generation for delay testing and dynamic timing analysisconsidering power-supply noise effects. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20 (3) (2001)
Jing-Jia Liou, Angela Krstic, Yi-Min Jiang, Kwang-Ting Cheng
Path Selection and Pattern Generation for Dynamic Timing Analysis Considering Power Supply Noise Effects. ICCAD (2000)
Yi-Min Jiang, Angela Krstic, Kwang-Ting Cheng
Estimation for maximum instantaneous current through supply lines for CMOS circuits. IEEE Trans. Very Large Scale Integr. Syst. 8 (1) (2000)
Yi-Min Jiang, Angela Krstic, Kwang-Ting Cheng
Dynamic Timing Analysis Considering Power Supply Noise Effects. ISQED (2000)
Yi-Min Jiang, Angela Krstic, Kwang-Ting Cheng
Delay testing considering power supply noise effects. ITC (1999)
Yi-Min Jiang, Tak K. Young, Kwang-Ting Cheng
VIP - an input pattern generator for indentifying critical voltage drop for deep sub-micron designs. ISLPED (1999)
Yi-Min Jiang, Kwang-Ting Cheng
Analysis of Performance Impact Caused by Power Supply Noise in Deep Submicron Devices. DAC (1999)
Yi-Min Jiang, Shi-Yu Huang, Kwang-Ting Cheng, Deborah C. Wang, ChingYen Ho
A Hybrid Power Model for RTL Power Estimation. ASP-DAC (1998)
Yi-Min Jiang, Kwang-Ting Cheng, An-Chang Deng
Estimation of maximum power supply noise for deep sub-micron designs. ISLPED (1998)
Yi-Min Jiang, Kwang-Ting Cheng
Exact and Approximate Estimation for Maximum Instantaneous Current of CMOS Circuits. DATE (1998)
Yi-Min Jiang, Angela Krstic, Kwang-Ting Cheng, Malgorzata Marek-Sadowska
Post-Layout Logic Restructuring for Performance Optimization. DAC (1997)
Yi-Min Jiang, Tsing-Fa Lee, TingTing Hwang, Youn-Long Lin
Performance-driven interconnection optimization for microarchitecture synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13 (2) (1994)
Yi-Min Jiang, Tsing-Fa Lee, TingTing Hwang, Yaun-Long Lin
Performance-driven interconnection optimization for microarchitecture synthesis. EURO-DAC (1992)