M. Ray Mercer

Publication Activity (10 Years)

Years Active: 1981-2005
Publications (10 Years): 0

Publications

Yuxin Tian, Michael R. Grimaila, Weiping Shi, M. Ray Mercer
An optimal test pattern selection method to improve the defect coverage. ITC (2005)
Jennifer Dworak, James Wingfield, M. Ray Mercer
A Preliminary Investigation of Observation Diversity for Enhancing Fortuitous Detection of Defects. DFT (2004)
Jennifer Dworak, Brad Cobb, James Wingfield, M. Ray Mercer
Balanced Excitation and Its Effect on the Fortuitous Detection of Dynamic Defects. DATE (2004)
Jennifer Dworak, David Dorsey, Amy Wang, M. Ray Mercer
Excitation, Observation, and ELF-MD: Optimization Criteria for High Quality Test Sets. VTS (2004)
Li-C. Wang, Angela Krstic, Leonard Lee, Kwang-Ting Cheng, M. Ray Mercer, Thomas W. Williams, Magdy S. Abadir
Using Logic Models To Predict The Detection Behavior Of Statistical Timing Defects. ITC (2003)
Yuxin Tian, Michael R. Grimaila, Weiping Shi, M. Ray Mercer
Minimizing Defective Part Level Using a Linear Programming-Based Optimal Test Selection Method. Asian Test Symposium (2003)
James Wingfield, Jennifer Dworak, M. Ray Mercer
Function-Based Dynamic Compaction and its Impact on Test Set Sizes. DFT (2003)
Jing-Jia Liou, Li-C. Wang, Kwang-Ting Cheng, Jennifer Dworak, M. Ray Mercer, Rohit Kapur, Thomas W. Williams
Enhancing test efficiency for delay fault testing using multiple-clocked schemes. DAC (2002)
Jing-Jia Liou, Li-C. Wang, Kwang-Ting Cheng, Jennifer Dworak, M. Ray Mercer, Rohit Kapur, Thomas W. Williams
Analysis of Delay Test Effectiveness with a Multiple-Clock Scheme. ITC (2002)
Rohit Kapur, Thomas W. Williams, M. Ray Mercer
Directed-Binary Search in Logic BIST Diagnostics. DATE (2002)
Jennifer Dworak, James Wingfield, Brad Cobb, Sooryong Lee, Li-C. Wang, M. Ray Mercer
Fortuitous Detection and its Impact on Test Set Sizes Using Stuck-at and Transition Faults. DFT (2002)
Sooryong Lee, Brad Cobb, Jennifer Dworak, Michael R. Grimaila, M. Ray Mercer
A New ATPG Algorithm to Limit Test Set Size and Achieve Multiple Detections of All Faults. DATE (2002)
Jennifer Dworak, Jason D. Wicker, Sooryong Lee, Michael R. Grimaila, M. Ray Mercer, Kenneth M. Butler, Bret Stewart, Li-C. Wang
Defect-Oriented Testing and Defective-Part-Level Prediction. IEEE Des. Test Comput. 18 (1) (2001)
Jennifer Dworak, Michael R. Grimaila, Sooryong Lee, Li-C. Wang, M. Ray Mercer
Enhanced DO-RE-ME based defect level prediction using defect site aggregation-MPG-D. ITC (2000)
Jennifer Dworak, Michael R. Grimaila, Brad Cobb, Ting-Chi Wang, Li-C. Wang, M. Ray Mercer
On the superiority of DO-RE-ME/MPG-D over stuck-at-based defective part level prediction. Asian Test Symposium (2000)
Ronald W. Mehler, M. Ray Mercer
Multi-Level Logic Minimization through Fault Dictionary Analysis. ICCD (1999)
Michael R. Grimaila, Sooryong Lee, Jennifer Dworak, Kenneth M. Butler, Bret Stewart, Hari Balachandran, Bryan Houchins, Vineet Mathur, Jaehong Park, Li-C. Wang, M. Ray Mercer
REDO - Probabilistic Excitation and Deterministic Observation - First Commercial Experimen. VTS (1999)
Jennifer Dworak, Michael R. Grimaila, Sooryong Lee, Li-C. Wang, M. Ray Mercer
Modeling the probability of defect excitation for a commercial IC with implications for stuck-at fault-based ATPG strategies. ITC (1999)
Thomas W. Williams, Robert H. Dennard, Rohit Kapur, M. Ray Mercer, Wojciech Maly
Test: Sensitivity Analysis of Scaling. ITC (1996)
Li-C. Wang, M. Ray Mercer, Thomas W. Williams
A Better ATPG Algorithm and Its Design Principles. ICCD (1996)
Thomas W. Williams, Rohit Kapur, M. Ray Mercer, Robert H. Dennard, Wojciech Maly
Iddq Testing for High Performance CMOS - The Next Ten Years. ED&TC (1996)
Chanhee Oh, M. Ray Mercer
Efficient logic-level timing analysis using constraint-guided critical path search. IEEE Trans. Very Large Scale Integr. Syst. 4 (3) (1996)
Jaehong Park, M. Ray Mercer
Using Functional Information and Strategy Switching in Sequential ATPG. ICCD (1996)
Li-C. Wang, M. Ray Mercer, Thomas W. Williams
Using Target Faults To Detect Non-Tartget Defects. ITC (1996)
Li-C. Wang, M. Ray Mercer, Sophia W. Kao, Thomas W. Williams
On the decline of testing efficiency as fault coverage approaches 100%. VTS (1995)
Li-C. Wang, M. Ray Mercer, Thomas W. Williams
On Efficiently and Reliably Achieving Low Defective Part Levels. ITC (1995)
Li-C. Wang, M. Ray Mercer, Thomas W. Williams
Enhanced testing performance via unbiased test sets. ED&TC (1995)
Jaehong Park, Chanhee Oh, M. Ray Mercer
Improved sequential ATPG using functional observation information and new justification methods. ED&TC (1995)
Ronn B. Brashear, Noel Menezes, Chanhee Oh, Lawrence T. Pillage, M. Ray Mercer
Predicting Circuit Performance Using Circuit-level Statistical Timing Analysis. EDAC-ETC-EUROASIC (1994)
Mark A. Heap, M. Ray Mercer
Least Upper Bounds an OBDD Sizes. IEEE Trans. Computers 43 (6) (1994)
Jaehong Park, Mark Naivar, Rohit Kapur, M. Ray Mercer, Thomas W. Williams
Limitations in predicting defect level based on stuck-at fault coverage. VTS (1994)
Jaehong Park, M. Ray Mercer
An Efficient Symbolic Design Verification System. ICCD (1993)
Eun Sei Park, M. Ray Mercer
Switch-Level ATPG Using Constraint-Guided Line Justification. ITC (1993)
Sanjay Srinivasan, Gnanasekaran Swaminathan, James H. Aylor, M. Ray Mercer
Combinational circuit ATPG using binary decision diagrams. VTS (1993)
Rohit Kapur, M. Ray Mercer
Bounding Signal Probabilities for Testability Measurement Using Conditional Syndromes. IEEE Trans. Computers 41 (12) (1992)
Mark A. Heap, William A. Rogers, M. Ray Mercer
A Synthesis Algorithm for Two-Level XOR Based Circuits. ICCD (1992)
Eun Sei Park, M. Ray Mercer, Thomas W. Williams
The Total Delay Fault Model and Statistical Delay Fault Coverage. IEEE Trans. Computers 41 (6) (1992)
Ronn B. Brashear, Douglas R. Holberg, M. Ray Mercer, Lawrence T. Pillage
ETA: electrical-level timing analysis. ICCAD (1992)
Rohit Kapur, Jaehong Park, M. Ray Mercer
All Tests for a Fault Are Not Equally Valuable for Defect Detection. ITC (1992)
M. Ray Mercer, Rohit Kapur, Don E. Ross
Functional Approaches to Generating Orderings for Efficient Symbolic Representations. DAC (1992)
Eun Sei Park, M. Ray Mercer
An efficient delay test generation system for combinational logic circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11 (7) (1992)
Kenneth M. Butler, Rohit Kapur, M. Ray Mercer, Don E. Ross
The roles of controllability and observability in design for test. VTS (1992)
Eun Sei Park, Bill Underwood, Thomas W. Williams, M. Ray Mercer
Delay Testing Quality in Timing-Optimized Designs. ITC (1991)
M. Ray Mercer
Testing and Design Verification of Electronic Components. Computer 24 (9) (1991)
Don E. Ross, Kenneth M. Butler, Rohit Kapur, M. Ray Mercer
Fast functional evaluation of candidate OBDD variable orderings. EURO-DAC (1991)
Don E. Ross, Kenneth M. Butler, M. Ray Mercer
Exact ordered binary decision diagram size when representing classes of symmetric functions. J. Electron. Test. 2 (3) (1991)
Thomas W. Williams, Bill Underwood, M. Ray Mercer
The Interdependence Between Delay-Optimization of Synthesized Networks and Testing. DAC (1991)
Kenneth M. Butler, Don E. Ross, Rohit Kapur, M. Ray Mercer
Heuristics to Compute Variable Orderings for Efficient Manipulation of Ordered Binary Decision Diagrams. DAC (1991)
Kenneth M. Butler, M. Ray Mercer
The Influences of Fault Type and Topology on Fault Model Performance and the Implications to Test and Testable Design. DAC (1990)
Eun Sei Park, M. Ray Mercer
An Efficient Delay Test Generation System for Combinational Logic Circuits. DAC (1990)
M. Ray Mercer
Guest Editorial: ITC 20th Anniversary. IEEE Des. Test Comput. 7 (2) (1990)
Eun Sei Park, M. Ray Mercer, Thomas W. Williams
A statistical model for delay-fault testing. IEEE Des. Test 6 (1) (1989)
C. Thomas Glover, M. Ray Mercer
A Deterministic Approach to Adjacency Testing for Delay Faults. DAC (1989)
Rhonda Kay Gaede, Don E. Ross, M. Ray Mercer, Kenneth M. Butler
CATAPULT: Concurrent Automatic Testing Allowing Parallelization and Using Limited Topology. DAC (1988)
Eun Sei Park, Thomas W. Williams, M. Ray Mercer
Statistical Delay Fault Coverage and Defect Level for Delay Faults. ITC (1988)
C. Thomas Glover, M. Ray Mercer
A Method of Delay Fault Test Generation. DAC (1988)
Steven P. Smith, Bill Underwood, M. Ray Mercer
D^3FS: A Demand Driven Deductive Fault Simulator. ITC (1988)
Tom E. Kirkland, M. Ray Mercer
Algorithms for automatic test pattern generation. IEEE Des. Test 5 (3) (1988)
Tom E. Kirkland, M. Ray Mercer
A Topological Search Algorithm for ATPG. DAC (1987)
Steven P. Smith, M. Ray Mercer, B. Brodk
Demand Driven Simulation: BACKSIM. DAC (1987)
Rhonda Kay Gaede, M. Ray Mercer, Bill Underwood
Calculation of Greatest Lower Bounds Obtainable by the Cutting Algorithm. ITC (1986)
M. Ray Mercer
Logic Elements for Universally Testable Circuits. ITC (1986)
Ki Soo Hwang, M. Ray Mercer
Derivation and Refinement of Fan-Out Constraints to Generate Tests in Combinational Logic Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 5 (4) (1986)
Ki Soo Hwang, M. Ray Mercer
Informed Test Generation Guidance Using Partially Specified Fanout Constraints. ITC (1986)
Tom E. Kirkland, M. Ray Mercer
A Two-Level Guidance Heuristic for ATPG. FJCC (1986)
Vishwani D. Agrawal, M. Ray Mercer
Deterministic Versus Random Testing. ITC (1986)
Eric Schell, M. Ray Mercer
CADTOOLS: a CAD algorithm development system. DAC (1985)
John Salick, Bill Underwood, M. Ray Mercer
Built-In Self Test Input Generator for Programmable Logic Arrays. ITC (1985)
Bill Underwood, M. Ray Mercer
Correlating Testability with Fault Detection. ITC (1984)
M. Ray Mercer
Testing Issues at the University of Texas. ITC (1983)
Vishwani D. Agrawal, M. Ray Mercer
Testability Measures : What Do They Tell Us ? ITC (1982)
M. Ray Mercer, Vishwani D. Agrawal, Carlos M. Roman
Test Generation for Highly Sequential Scan-Testable Circuits Through Logic Transformation. ITC (1981)