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Derivation and Refinement of Fan-Out Constraints to Generate Tests in Combinational Logic Circuits.

Ki Soo HwangM. Ray Mercer
Published in: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (1986)
Keyphrases
  • logic circuits
  • low power
  • functional decomposition
  • tunnel diode
  • logic synthesis
  • high speed
  • power consumption
  • constraint programming
  • gate array
  • low cost
  • computer vision