Eun Sei Park

Publication Activity (10 Years)

Years Active: 1988-1998
Publications (10 Years): 0

Publications

Byunggyu Kwak, Eun Sei Park
An Optimization-Based Error Calculation for Statistical Power Estimation of CMOS Logic Circuits. DAC (1998)
Sung Tae Jung, Eun Sei Park, Jung Sik Kim, Chu Shik Jhon
Automatic Synthesis of Gate-Level Speed-Independent Control Circuits from Signal Transition Graphs. ISCAS (1995)
Eun Sei Park, M. Ray Mercer
Switch-Level ATPG Using Constraint-Guided Line Justification. ITC (1993)
Eun Sei Park, M. Ray Mercer, Thomas W. Williams
The Total Delay Fault Model and Statistical Delay Fault Coverage. IEEE Trans. Computers 41 (6) (1992)
Eun Sei Park, M. Ray Mercer
An efficient delay test generation system for combinational logic circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11 (7) (1992)
Eun Sei Park, Bill Underwood, Thomas W. Williams, M. Ray Mercer
Delay Testing Quality in Timing-Optimized Designs. ITC (1991)
Eun Sei Park, M. Ray Mercer
An Efficient Delay Test Generation System for Combinational Logic Circuits. DAC (1990)
Eun Sei Park, M. Ray Mercer, Thomas W. Williams
A statistical model for delay-fault testing. IEEE Des. Test 6 (1) (1989)
Eun Sei Park, Thomas W. Williams, M. Ray Mercer
Statistical Delay Fault Coverage and Defect Level for Delay Faults. ITC (1988)