An efficient delay test generation system for combinational logic circuits.
Eun Sei ParkM. Ray MercerPublished in: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (1992)
Keyphrases
- logic circuits
- test generation
- low power
- power dissipation
- test cases
- test sequences
- functional decomposition
- power consumption
- static analysis
- symbolic execution
- tunnel diode
- quality assurance
- gate array
- logic synthesis
- low cost
- software testing
- design automation
- high speed
- decision trees
- digital signal processing
- test suite
- relational databases
- real time