An Optimization-Based Error Calculation for Statistical Power Estimation of CMOS Logic Circuits.

Byunggyu Kwak Eun Sei Park

Published in: DAC (1998)

Keyphrases

statistical power
type i error
logic circuits
low power
statistical significance
low cost
high speed
sample size
power dissipation
power consumption
registration errors
interaction effects
image processing
pattern recognition
type ii
computer vision
tunnel diode
gate array