An Efficient Delay Test Generation System for Combinational Logic Circuits.

Eun Sei Park M. Ray Mercer

Published in: DAC (1990)

Keyphrases

logic circuits
test generation
low power
power dissipation
test cases
symbolic execution
functional decomposition
power consumption
test sequences
design automation
gate array
tunnel diode
logic synthesis
high speed
quality assurance
static analysis
low cost
test set
training data