T. M. Mak

Publication Activity (10 Years)

Years Active: 1998-2020
Publications (10 Years): 2

Top Topics

Set Of Test Cases

Printed Circuit Boards

Item Response Theory

Gigabit Ethernet

Top Venues

IEEE Instrum. Meas. Mag.

J. Electron. Test.

ACM Trans. Design Autom. Electr. Syst.

Publications

Louis Y. Ungar, Neil G. Jacobson, T. M. Mak
High-speed I/O capabilities added to military automatic test equipment (ATE) using synthetic instruments. IEEE Instrum. Meas. Mag. 23 (5) (2020)
Jae Woong Jeong, Vishwanath Natarajan, Shreyas Sen, T. M. Mak, Jennifer Kitchen, Sule Ozev
A Comprehensive BIST Solution for Polar Transceivers Using On-Chip Resources. ACM Trans. Design Autom. Electr. Syst. 23 (1) (2017)
Martin Omaña, Daniele Rossi, Daniele Giaffreda, Cecilia Metra, T. M. Mak, Asifur Rahman, Simon Tam
Low-Cost On-Chip Clock Jitter Measurement Scheme. IEEE Trans. Very Large Scale Integr. Syst. 23 (3) (2015)
John Kim, Wolfgang Meyer, T. M. Mak, Amitava Majumdar
Innovative practices session 3C: Solving today's test challenges. VTS (2014)
T. M. Mak
Interposer test: Testing PCBs that have shrunk 100x. ITC (2014)
Daniele Rossi, Martin Omaña, José Manuel Cazeaux, Cecilia Metra, T. M. Mak
Clock Faults Induced Min and Max Delay Violations. J. Electron. Test. 30 (1) (2014)
Jae Woong Jeong, Sule Ozev, Shreyas Sen, T. M. Mak
Measurement of envelope/phase path delay skew and envelope path bandwidth in polar transmitters. VTS (2013)
Cecilia Metra, Martin Omaña, T. M. Mak, Simon Tam
New Design for Testability Approach for Clock Fault Testing. IEEE Trans. Computers 61 (4) (2012)
Li Jiang, Qiang Xu, Krishnendu Chakrabarty, T. M. Mak
Integrated Test-Architecture Optimization and Thermal-Aware Test Scheduling for 3-D SoCs Under Pre-Bond Test-Pin-Count Constraint. IEEE Trans. Very Large Scale Integr. Syst. 20 (9) (2012)
Martin Omaña, Cecilia Metra, T. M. Mak, Simon Tam
Low-Cost Dynamic Compensation Scheme for Local Clocks of Next Generation High Performance Microprocessors. IEEE Trans. Very Large Scale Integr. Syst. 19 (12) (2011)
Martin Omaña, Daniele Giaffreda, Cecilia Metra, T. M. Mak, Simon Tam, Asifur Rahman
On-die Ring Oscillator Based Measurement Scheme for Process Parameter Variations and Clock Jitter. DFT (2010)
Joon-Sung Yang, Nur A. Touba, Shih-Yu Yang, T. M. Mak
An industrial case study for X-canceling MISR. ITC (2009)
Li Jiang, Qiang Xu, Krishnendu Chakrabarty, T. M. Mak
Layout-driven test-architecture design and optimization for 3D SoCs under pre-bond test-pin-count constraint. ICCAD (2009)
Cecilia Metra, Martin Omaña, T. M. Mak, Asifur Rahman, Simon Tam
Novel On-Chip Clock Jitter Measurement Scheme for High Performance Microprocessors. DFT (2008)
T. M. Mak
Jitters in high performance microprocessors. ITC (2008)
T. M. Mak
Invited Talk 1: Testing of Power Constraint Computing. ATS (2007)
Cecilia Metra, Martin Omaña, T. M. Mak, Simon Tam
Novel compensation scheme for local clocks of high performance microprocessors. ITC (2007)
T. M. Mak
The case for power with test. IEEE Des. Test Comput. 24 (3) (2007)
Cecilia Metra, Martin Omaña, T. M. Mak, Simon Tam
Novel Approach to Clock Fault Testing for High Performance Microprocessors. VTS (2007)
T. M. Mak
Infant Mortality--The Lesser Known Reliability Issue. IOLTS (2007)
Ming Zhang, T. M. Mak, James W. Tschanz, Kee Sup Kim, Norbert Seifert, Davia Lu
Design for Resilience to Soft Errors and Variations. IOLTS (2007)
Cecilia Metra, Daniele Rossi, T. M. Mak
Won't On-Chip Clock Calibration Guarantee Performance Boost and Product Quality?. IEEE Trans. Computers 56 (3) (2007)
Rajesh Thirugnanam, Dong Sam Ha, T. M. Mak
Data Recovery Block Design for Impulse Modulated Power Line Communications in a Microprocessor. ISVLSI (2007)
Kaushik Roy, T. M. Mak, Kwang-Ting (Tim) Cheng
Test Consideration for Nanometer-Scale CMOS Circuits. IEEE Des. Test Comput. 23 (2) (2006)
Cecilia Metra, Martin Omaña, Daniele Rossi, José Manuel Cazeaux, T. M. Mak
Path (Min) Delay Faults and Their Impact on Self-Checking Circuits' Operation. IOLTS (2006)
Ming Zhang, Subhasish Mitra, T. M. Mak, Norbert Seifert, Nicholas J. Wang, Quan Shi, Kee Sup Kim, Naresh R. Shanbhag, Sanjay J. Patel
Sequential Element Design With Built-In Soft Error Resilience. IEEE Trans. Very Large Scale Integr. Syst. 14 (12) (2006)
T. M. Mak
Is System in Package the Panacea for Integration? IEEE Des. Test Comput. 23 (3) (2006)
Maryam Ashouei, Abhijit Chatterjee, Adit D. Singh, Vivek De, T. M. Mak
Statistical Estimation of Correlated Leakage Power Variation and Its Application to Leakage-Aware Design. VLSI Design (2006)
T. M. Mak, Subhasish Mitra
Should Logic SER be Solved at the Circuit Level? IOLTS (2006)
T. M. Mak
Test Challenges for 3D Circuits. IOLTS (2006)
Subhasish Mitra, Ming Zhang, Norbert Seifert, T. M. Mak, Kee Sup Kim
Soft Error Resilient System Design through Error Correction. VLSI-SoC (2006)
T. M. Mak, Sani R. Nassif
Guest Editors' Introduction: Process Variation and Stochastic Design and Test. IEEE Des. Test Comput. 23 (6) (2006)
Subhasish Mitra, Ming Zhang, Norbert Seifert, T. M. Mak, Kee Sup Kim
Soft Error Resilient System Design through Error Correction. VLSI-SoC (Selected Papers) (2006)
Cecilia Metra, Daniele Rossi, Martin Omaña, José Manuel Cazeaux, T. M. Mak
Can Clock Faults be Detected Through Functional Test? DDECS (2006)
Arani Sinha, Shahin Nazarian, T. M. Mak
Simulating the Effects of Process Variations on Capacitive Crosstalk. ICECS (2006)
Subhasish Mitra, Ming Zhang, T. M. Mak, Norbert Seifert, Victor Zia, Kee Sup Kim
Logic soft errors: a major barrier to robust platform design. ITC (2005)
T. M. Mak
Does It Mean Less Testing for Self Calibrating Design?. IOLTS (2005)
T. M. Mak
Limitation of structural scan delay test. Asian Test Symposium (2005)
Cecilia Metra, Martin Omaña, Daniele Rossi, José Manuel Cazeaux, T. M. Mak
The Other Side of the Timing Equation: a Result of Clock Faults. DFT (2005)
Leonard Lee, Li-C. Wang, Praveen Parvathala, T. M. Mak
On Silicon-Based Speed Path Identification. VTS (2005)
T. M. Mak, Subhasish Mitra, Ming Zhang
DFT Assisted Built-In Soft Error Resilience. IOLTS (2005)
Eric F. Weglarz, Kewal K. Saluja, T. M. Mak
Testing of Hard Faults in Simultaneous Multithreaded Processors. IOLTS (2004)
Leonard Lee, Li-C. Wang, T. M. Mak, Kwang-Ting Cheng
A path-based methodology for post-silicon timing validation. ICCAD (2004)
Michael Spica, T. M. Mak
Do We Need Anything More Than Single Bit Error Correction (ECC)? MTDT (2004)
Cecilia Metra, T. M. Mak, Martin Omaña
Are Our Design for Testability Features Fault Secure? DATE (2004)
Melvin A. Breuer, Sandeep K. Gupta, T. M. Mak
Defect and Error Tolerance in the Presence of Massive Numbers of Defects. IEEE Des. Test Comput. 21 (3) (2004)
Cecilia Metra, T. M. Mak, Martin Omaña
Risks Associated with Faults within Test Pattern Compactors and Their Implications on Testing. ITC (2004)
Cecilia Metra, T. M. Mak, Martin Omaña
Fault secureness need for next generation high performance microprocessor design for testability structures. Conf. Computing Frontiers (2004)
Mike Tripp, T. M. Mak, Anne Meixner
Elimination of Traditional Functional Testing of Interface Timings at Intel. ITC (2004)
Li-C. Wang, T. M. Mak, Kwang-Ting Cheng, Magdy S. Abadir
On path-based learning and its applications in delay test and diagnosis. DAC (2004)
Cecilia Metra, Stefano Di Francescantonio, T. M. Mak
Implications of Clock Distribution Faults and Issues with Screening Them during Manufacturing Testing. IEEE Trans. Computers 53 (5) (2004)
Sandip Kundu, T. M. Mak, Rajesh Galivanche
Trends in manufacturing test methods and their implications. ITC (2004)
T. M. Mak, Mike Tripp, Anne Meixner
Testing Gbps Interfaces without a Gigahertz Tester. IEEE Des. Test Comput. 21 (4) (2004)
T. M. Mak, Angela Krstic, Kwang-Ting (Tim) Cheng, Li-C. Wang
New Challenges in Delay Testing of Nanometer, Multigigahertz Designs. IEEE Des. Test Comput. 21 (3) (2004)
Mike Tripp, T. M. Mak, Anne Meixner
Design considerations and DFT to enable testing of digital interfaces. CICC (2004)
Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, Jing-Jia Liou, T. M. Mak
Enhancing diagnosis resolution for delay defects based upon statistical timing and statistical fault models. DAC (2003)
Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, T. M. Mak
Diagnosis-Based Post-Silicon Timing Validation Using Statistical Tools and Methodologies. ITC (2003)
Cecilia Metra, T. M. Mak, Daniele Rossi
Clock Calibration Faults and their Impact on Quality of High Performance Microprocessors. DFT (2003)
Kaushik Roy, T. M. Mak, Kwang-Ting Cheng
Embedded Tutorial: Test Consideration for Nanometer Scale CMOS Circuits. VTS (2003)
Mike Tripp, T. M. Mak, Anne Meixner
Elimination of Traditional Functional Testing of Interface Timings at Intel. ITC (2003)
Cecilia Metra, Stefano Di Francescantonio, T. M. Mak
Clock Faults? Impact on Manufacturing Testing and Their Possible Detection Through On-Line Testing. ITC (2002)
Liang-Chi Chen, T. M. Mak, Sandeep K. Gupta, Melvin A. Breuer
Crosstalk test generation on pseudo industrial circuits: a case study. ITC (2001)
Cecilia Metra, Stefano Di Francescantonio, Bruno Riccò, T. M. Mak
Evaluation of Clock Distribution Networks' Most Likely Faults and Produced Effects. DFT (2001)
T. M. Mak, Debika Bhattacharya, Cheryl Prunty, Bob Roeder, Nermine Ramadan, F. Joel Ferguson, Jianlin Yu
Cache RAM inductive fault analysis with fab defect modeling. ITC (1998)