Simon Tam

Publication Activity (10 Years)

Years Active: 2000-2015
Publications (10 Years): 0

Top Topics

Vlsi Implementation

Transient Response

Electrical Power

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Martin Omaña, Daniele Rossi, Daniele Giaffreda, Cecilia Metra, T. M. Mak, Asifur Rahman, Simon Tam
Low-Cost On-Chip Clock Jitter Measurement Scheme. IEEE Trans. Very Large Scale Integr. Syst. 23 (3) (2015)
Selçuk Köse, Simon Tam, Sally Pinzon, Bruce McDermott, Eby G. Friedman
Active Filter-Based Hybrid On-Chip DC-DC Converter for Point-of-Load Voltage Regulation. IEEE Trans. Very Large Scale Integr. Syst. 21 (4) (2013)
Cecilia Metra, Martin Omaña, T. M. Mak, Simon Tam
New Design for Testability Approach for Clock Fault Testing. IEEE Trans. Computers 61 (4) (2012)
Martin Omaña, Cecilia Metra, T. M. Mak, Simon Tam
Low-Cost Dynamic Compensation Scheme for Local Clocks of Next Generation High Performance Microprocessors. IEEE Trans. Very Large Scale Integr. Syst. 19 (12) (2011)
Martin Omaña, Daniele Giaffreda, Cecilia Metra, T. M. Mak, Simon Tam, Asifur Rahman
On-die Ring Oscillator Based Measurement Scheme for Process Parameter Variations and Clock Jitter. DFT (2010)
Cecilia Metra, Martin Omaña, T. M. Mak, Asifur Rahman, Simon Tam
Novel On-Chip Clock Jitter Measurement Scheme for High Performance Microprocessors. DFT (2008)
Cecilia Metra, Martin Omaña, T. M. Mak, Simon Tam
Novel compensation scheme for local clocks of high performance microprocessors. ITC (2007)
Cecilia Metra, Martin Omaña, T. M. Mak, Simon Tam
Novel Approach to Clock Fault Testing for High Performance Microprocessors. VTS (2007)
Simon Tam, Justin Leung, Rahul Dilip Limaye, Sam Choy, Sujal Vora, Mitsuhiro Adachi
Clock Generation and Distribution of a Dual-Core Xeon Processor with 16MB L3 Cache. ISSCC (2006)
Jonathan Chang, Stefan Rusu, Jonathan Shoemaker, Simon Tam, Ming Huang, Mizan Haque, Siufu Chiu, Kevin Truong, Mesbah Karim, Gloria Leong, Kiran Desai, Richard Goe, Sandhya Kulkarni
A 130-nm triple-V/sub t/ 9-MB third-level on-die cache for the 1.7-GHz Itanium/spl reg/ 2 processor. IEEE J. Solid State Circuits 40 (1) (2005)
Simon Tam, Rahul Dilip Limaye, Utpal Nagarji Desai
2 processor with 6-MB on-die L3 cache. IEEE J. Solid State Circuits 39 (4) (2004)
Stefan Rusu, Jason Stinson, Simon Tam, Justin Leung, Harry Muljono, Brian S. Cherkauer
A 1.5-GHz 130-nm Itanium® 2 Processor with 6-MB on-die L3 cache. IEEE J. Solid State Circuits 38 (11) (2003)
Simon Tam, Stefan Rusu, Utpal Nagarji Desai, Robert Kim, Ji Zhang, Ian Young
Clock generation and distribution for the first IA-64 microprocessor. IEEE J. Solid State Circuits 35 (11) (2000)