Daniele Rossi

Publication Activity (10 Years)

Years Active: 2002-2024
Publications (10 Years): 32

Top Topics

Leakage Current

Bias Variance Decomposition

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Vasileios Tenentes, Stefano Di Matteo, Christos Zonios, Daniele Rossi, Sergio Saponara
RTL Flow for the Power Side-Channel Resilience Assessment of a Post-Quantum SHA-3 Accelerator. MOCAST (2024)
Gabriele Ciarpi, Marco Mestice, Daniele Rossi, Fabrizio Palla, Sergio Saponara
10 Gb/s Line Driver in 65 nm CMOS Technology for Radiation Environments. ICECS (2023)
Daniele Rossi, Nicasio Canino, Stefano Di Matteo, Sergio Saponara, Vasileios Tenentes
Design and Evaluation of a Peripheral for Integrity Checking to Improve RAS in RISC-V Architectures. SEEDA-CECNSM (2023)
Vasileios Tenentes, Athanasios Xynos, Christos Zonios, Asimina Koutra, Christina Dilopoulou, Konstantinos Tsampiras, Yiorgos Tsiatouhas, Daniele Rossi
Embedded Platforms for Trusted Edge Computing Towards Quality Assurance Along the Supply Chain. SEEDA-CECNSM (2023)
Gabriele Ciarpi, Ettore Noccetti, Luca Ceragioli, Marco Mestice, Daniele Rossi, Sergio Saponara
Smart Kinetic Floor System for Energy Harvesting and Data Acquisition in High Foot-Traffic Areas. ApplePies (2023)
Gabriele Ciarpi, Marco Mestice, Daniele Rossi, Fabrizio Palla, Sergio Saponara
A 10 Gb/s Line Driver in 65 nm CMOS Technology for Radiation-Pervaded and High-Temperature Applications. IEEE Access 11 (2023)
Gabriele Ciarpi, Marco Mestice, Daniele Rossi, Sergio Saponara
Wire Bonding: Limitations and Opportunities for High-Speed Serial Communications. ApplePies (2023)
Antonio Leonel Hernández Martínez, Saqib Khursheed, Turki Alnuayri, Daniele Rossi
Online Remaining Useful Lifetime Prediction Using Support Vector Regression. IEEE Trans. Emerg. Top. Comput. 10 (3) (2022)
Marco Mestice, G. Biondi, Gabriele Ciarpi, Daniele Rossi, Sergio Saponara
A Low-Area, Low-Power, Wide Tuning Range Digitally Controlled Oscillator for Power Management Systems in 28 nm CMOS Technology. ApplePies (2022)
Marco Grossi, Martin Omaña, Daniele Rossi, Biagio Marzulli, Cecilia Metra
Novel BTI Robust Ring-Oscillator-Based Physically Unclonable Function. IOLTS (2022)
Gabriele Ciarpi, G. Puccioni, Marco Mestice, Danilo Monda, Daniele Rossi, Sergio Saponara
A 2 GHz Wide Tuning Range LC-Tank Digitally Controlled Oscillator in 28 nm CMOS Technology. ApplePies (2022)
Gor Piliposyan, Saqib Khursheed, Daniele Rossi
Hardware Trojan Detection on a PCB Through Differential Power Monitoring. IEEE Trans. Emerg. Top. Comput. 10 (2) (2022)
Turki Alnuayri, S. Saqib Khursheed, Antonio Leonel Hernández Martínez, Daniele Rossi
Differential Aging Sensor Using Subthreshold Leakage Current to Detect Recycled ICs. IEEE Trans. Very Large Scale Integr. Syst. 29 (12) (2021)
Turki Alnuayri, S. Saqib Khursheed, Antonio Leonel Hernández Martínez, Daniele Rossi
Differential Aging Sensor to Detect Recycled ICs using Sub-threshold Leakage Current. DATE (2021)
Antonio Leonel Hernández Martínez, S. Saqib Khursheed, Daniele Rossi
Leveraging CMOS Aging for Efficient Microelectronics Design. IOLTS (2020)
Abdessamad Najdi, Daniele Rossi, Vasileios Tenentes
Analysis on Retention Time and Adaptive Refresh in Embedded DRAMs with Aging Benefits. IOLTS (2019)
Vasileios Tenentes, Shidhartha Das, Daniele Rossi, Bashir M. Al-Hashimi
Run-time Detection and Mitigation of Power-Noise Viruses. IOLTS (2019)
Daniele Rossi, Vasileios Tenentes, S. Saqib Khursheed, Sudhakar M. Reddy
Recycled IC detection through aging sensor. ETS (2018)
Vasileios Tenentes, Daniele Rossi, Bashir M. Al-Hashimi
Collective-Aware System-on-Chips for Dependable IoT Applications. IOLTS (2018)
Vasileios Tenentes, Daniele Rossi, S. Saqib Khursheed, Bashir M. Al-Hashimi, Krishnendu Chakrabarty
Leakage Current Analysis for Diagnosis of Bridge Defects in Power-Gating Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (4) (2018)
Daniele Rossi, Vasileios Tenentes, Sudhakar M. Reddy, Bashir M. Al-Hashimi, Andrew Brown
Exploiting Aging Benefits for the Design of Reliable Drowsy Cache Memories. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (7) (2018)
Mauricio D. Gutierrez, Vasileios Tenentes, Tom J. Kazmierski, Daniele Rossi
Low cost error monitoring for improved maintainability of IoT applications. DFT (2017)
Mauricio D. Gutierrez, Vasileios Tenentes, Tom J. Kazmierski, Daniele Rossi
Low power probabilistic online monitoring of systematic erroneous behaviour. ETS (2017)
Mauricio D. Gutierrez, Vasileios Tenentes, Daniele Rossi, Tom J. Kazmierski
Susceptible Workload Evaluation and Protection using Selective Fault Tolerance. J. Electron. Test. 33 (4) (2017)
Daniele Rossi, Vasileios Tenentes, Sheng Yang, Syed Saqib Khursheed, Bashir M. Al-Hashimi
Aging Benefits in Nanometer CMOS Designs. IEEE Trans. Circuits Syst. II Express Briefs (3) (2017)
Martin Omaña, Daniele Rossi, Filippo Fuzzi, Cecilia Metra, Chandra Tirumurti, Rajesh Galivanche
Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST. IEEE Trans. Very Large Scale Integr. Syst. 25 (1) (2017)
Vasileios Tenentes, Daniele Rossi, Sheng Yang, S. Saqib Khursheed, Bashir M. Al-Hashimi, Steve R. Gunn
Coarse-Grained Online Monitoring of BTI Aging by Reusing Power-Gating Infrastructure. IEEE Trans. Very Large Scale Integr. Syst. 25 (4) (2017)
Basel Halak, Vasileios Tenentes, Daniele Rossi
The impact of BTI aging on the reliability of level shifters in nano-scale CMOS technology. Microelectron. Reliab. 67 (2016)
Martin Omaña, Daniele Rossi, Edda Beniamino, Cecilia Metra, Chandrasekharan Tirumurti, Rajesh Galivanche
Low-Cost and High-Reduction Approaches for Power Droop during Launch-On-Shift Scan-Based Logic BIST. IEEE Trans. Computers 65 (8) (2016)
Jiajing Cai, Basel Halak, Daniele Rossi
Analysis of BTI aging of level shifters. IOLTS (2016)
Daniele Rossi, Vasileios Tenentes, Sheng Yang, S. Saqib Khursheed, Bashir M. Al-Hashimi
Reliable Power Gating With NBTI Aging Benefits. IEEE Trans. Very Large Scale Integr. Syst. 24 (8) (2016)
Hardeep Chahal, Vasileios Tenentes, Daniele Rossi, Bashir M. Al-Hashimi
BTI aware thermal management for reliable DVFS designs. DFT (2016)
Daniele Rossi, Vasileios Tenentes, S. Saqib Khursheed, Bashir M. Al-Hashimi
BTI and leakage aware dynamic voltage scaling for reliable low power cache memories. IOLTS (2015)
Vasileios Tenentes, Daniele Rossi, S. Saqib Khursheed, Bashir M. Al-Hashimi
Diagnosis of power switches with power-distribution-network consideration. ETS (2015)
Daniele Rossi, Vasileios Tenentes, S. Saqib Khursheed, Bashir M. Al-Hashimi
NBTI and leakage aware sleep transistor design for reliable and energy efficient power gating. ETS (2015)
Daniele Rossi, Martin Omaña, Cecilia Metra, Alessandro Paccagnella
Impact of Bias Temperature Instability on Soft Error Susceptibility. IEEE Trans. Very Large Scale Integr. Syst. 23 (4) (2015)
Martin Omaña, Daniele Rossi, Daniele Giaffreda, Cecilia Metra, T. M. Mak, Asifur Rahman, Simon Tam
Low-Cost On-Chip Clock Jitter Measurement Scheme. IEEE Trans. Very Large Scale Integr. Syst. 23 (3) (2015)
Vasileios Tenentes, S. Saqib Khursheed, Daniele Rossi, Sheng Yang, Bashir M. Al-Hashimi
DFT Architecture With Power-Distribution-Network Consideration for Delay-Based Power Gating Test. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34 (12) (2015)
Daniele Rossi, Martin Omaña, Daniele Giaffreda, Cecilia Metra
Modeling and Detection of Hotspot in Shaded Photovoltaic Cells. IEEE Trans. Very Large Scale Integr. Syst. 23 (6) (2015)
Martin Omaña, Daniele Rossi, Edda Beniamino, Cecilia Metra, Chandra Tirumurti, Rajesh Galivanche
Power droop reduction during Launch-On-Shift scan-based logic BIST. DFT (2014)
Daniele Rossi, Martin Omaña, José Manuel Cazeaux, Cecilia Metra, T. M. Mak
Clock Faults Induced Min and Max Delay Violations. J. Electron. Test. 30 (1) (2014)
Martin Omaña, Daniele Rossi, Nicolò Bosio, Cecilia Metra
Low Cost NBTI Degradation Detection and Masking Approaches. IEEE Trans. Computers 62 (3) (2013)
Martin Omaña, Daniele Rossi, Filippo Fuzzi, Cecilia Metra, Chandra Tirumurti, R. Galivache
Novel approach to reduce power droop during scan-based logic BIST. ETS (2013)
Martin Omaña, Daniele Rossi, Daniele Giaffreda, Roberto Specchia, Cecilia Metra, Marcin Marzencki, Bozena Kaminska
Faults Affecting Energy-Harvesting Circuits of Self-Powered Wireless Sensors and Their Possible Concurrent Detection. IEEE Trans. Very Large Scale Integr. Syst. 21 (12) (2013)
Daniele Rossi, Martin Omaña, G. Garrammone, Cecilia Metra, Abhijit Jas, Rajesh Galivanche
Low Cost Concurrent Error Detection Strategy for the Control Logic of High Performance Microprocessors and Its Application to the Instruction Decoder. J. Electron. Test. 29 (3) (2013)
Cristiana Bolchini, Antonio Miele, Chiara Sandionigi, Marco Ottavi, Salvatore Pontarelli, Adelio Salsano, Cecilia Metra, Martin Omaña, Daniele Rossi, Matteo Sonza Reorda, Luca Sterpone, Massimo Violante, Simone Gerardin, M. Bagatin, Alessandro Paccagnella
High-reliability fault tolerant digital systems in nanometric technologies: Characterization and design methodologies. DFT (2012)
Martin Omaña, Daniele Rossi, G. Collepalumbo, Cecilia Metra, Fabrizio Lombardi
Faults affecting the control blocks of PV arrays and techniques for their concurrent detection. DFT (2012)
Daniele Giaffreda, Martin Omaña, Daniele Rossi, Cecilia Metra
Model for Thermal Behavior of Shaded Photovoltaic Cells under Hot-Spot Condition. DFT (2011)
Daniele Rossi, N. Timoncini, M. Spica, Cecilia Metra
Error correcting code analysis for cache memory high reliability and performance. DATE (2011)
Daniele Rossi, Martin Omaña, Cecilia Metra, Alessandro Paccagnella
Impact of Aging Phenomena on Soft Error Susceptibility. DFT (2011)
Martin Omaña, Daniele Rossi, Cecilia Metra
High-Performance Robust Latches. IEEE Trans. Computers 59 (11) (2010)
Daniele Rossi, Martin Omaña, Gianluca Berghella, Cecilia Metra, Abhijit Jas, Chandra Tirumurti, Rajesh Galivanche
Low cost and low intrusive approach to test on-line the scheduler of high performance microprocessors. Conf. Computing Frontiers (2010)
Martin Omaña, Daniele Rossi, Nicolò Bosio, Cecilia Metra
Novel low-cost aging sensor. Conf. Computing Frontiers (2010)
Daniele Rossi, Martin Omaña, Daniele Giaffreda, Cecilia Metra
Secure communication protocol for wireless sensor networks. EWDTS (2010)
Daniele Rossi, Martin Omaña, Cecilia Metra
Transient Fault and Soft Error On-die Monitoring Scheme. DFT (2010)
Martin Omaña, Daniele Rossi, Cecilia Metra
Novel High Speed Robust Latch. DFT (2009)
Daniele Rossi, José Manuel Cazeaux, Martin Omaña, Cecilia Metra, Abhijit Chatterjee
Accurate Linear Model for SET Critical Charge Estimation. IEEE Trans. Very Large Scale Integr. Syst. 17 (8) (2009)
Daniele Rossi, Martin Omaña, Cecilia Metra
Checkers' No-Harm Alarms and Design Approaches to Tolerate Them. J. Electron. Test. 24 (1-3) (2008)
Daniele Rossi, André K. Nieuwland, Cecilia Metra
Simultaneous Switching Noise: The Relation between Bus Layout and Coding. IEEE Des. Test Comput. 25 (1) (2008)
Cecilia Metra, Daniele Rossi, Martin Omaña, Abhijit Jas, Rajesh Galivanche
Function-Inherent Code Checking: A New Low Cost On-Line Testing Approach for High Performance Microprocessor Control Logic. ETS (2008)
Daniele Rossi, Paolo Angelini, Cecilia Metra, Giovanni Campardo, Gian Pietro Vanalli
Risks for Signal Integrity in System in Package and Possible Remedies. ETS (2008)
Daniele Rossi, André K. Nieuwland, Steven V. E. S. van Dijk, Richard P. Kleihorst, Cecilia Metra
Power Consumption of Fault Tolerant Busses. IEEE Trans. Very Large Scale Integr. Syst. 16 (5) (2008)
Daniele Rossi, Paolo Angelini, Cecilia Metra
Configurable Error Control Scheme for NoC Signal Integrity. IOLTS (2007)
Martin Omaña, Daniele Rossi, Cecilia Metra
Latch Susceptibility to Transient Faults and New Hardening Approach. IEEE Trans. Computers 56 (9) (2007)
Cecilia Metra, Daniele Rossi, T. M. Mak
Won't On-Chip Clock Calibration Guarantee Performance Boost and Product Quality?. IEEE Trans. Computers 56 (3) (2007)
Cecilia Metra, Martin Omaña, Daniele Rossi, José Manuel Cazeaux, T. M. Mak
Path (Min) Delay Faults and Their Impact on Self-Checking Circuits' Operation. IOLTS (2006)
Daniele Rossi, Carlo Steiner, Cecilia Metra
Analysis of the impact of bus implemented EDCs on on-chip SSN. DATE (2006)
Daniele Rossi, Martin Omaña, Cecilia Metra, Andrea Pagni
Checker No-Harm Alarm Robustness. IOLTS (2006)
Martin Omaña, José Manuel Cazeaux, Daniele Rossi, Cecilia Metra
Low-cost and highly reliable detector for transient and crosstalk faults affecting FPGA interconnects. DATE (2006)
Cecilia Metra, Daniele Rossi, Martin Omaña, José Manuel Cazeaux, T. M. Mak
Can Clock Faults be Detected Through Functional Test? DDECS (2006)
Daniele Rossi, André K. Nieuwland, Atul Katoch, Cecilia Metra
Exploiting ECC Redundancy to Minimize Crosstalk Impact. IEEE Des. Test Comput. 22 (1) (2005)
Daniele Rossi, André K. Nieuwland, Atul Katoch, Cecilia Metra
New ECC for Crosstalk Impact Minimization. IEEE Des. Test Comput. 22 (4) (2005)
Martin Omaña, Daniele Rossi, Cecilia Metra
Low Cost Scheme for On-Line Clock Skew Compensation. VTS (2005)
José Manuel Cazeaux, Daniele Rossi, Martin Omaña, Cecilia Metra, Abhijit Chatterjee
On Transistor Level Gate Sizing for Increased Robustness to Transient Faults. IOLTS (2005)
André K. Nieuwland, Atul Katoch, Daniele Rossi, Cecilia Metra
Coding Techniques for Low Switching Noise in Fault Tolerant Busses. IOLTS (2005)
Cecilia Metra, Martin Omaña, Daniele Rossi, José Manuel Cazeaux, T. M. Mak
The Other Side of the Timing Equation: a Result of Clock Faults. DFT (2005)
Daniele Rossi, Martin Omaña, Fabio Toma, Cecilia Metra
Multiple Transient Faults in Logic: An Issue for Next Generation ICs. DFT (2005)
Martin Omaña, Daniele Rossi, Cecilia Metra
Low Cost and High Speed Embedded Two-Rail Code Checker. IEEE Trans. Computers 54 (2) (2005)
José Manuel Cazeaux, Daniele Rossi, Cecilia Metra
Self-Checking Voter for High Speed TMR Systems. J. Electron. Test. 21 (4) (2005)
José Manuel Cazeaux, Daniele Rossi, Cecilia Metra
New High Speed CMOS Self-Checking Voter. IOLTS (2004)
Daniele Rossi, A. Muccio, André K. Nieuwland, Atul Katoch, Cecilia Metra
Impact of ECCs on Simultaneously Switching Output Noise for On-Chip Busses of High Reliability Systems. IOLTS (2004)
Martin Omaña, Daniele Rossi, Cecilia Metra
Fast and Low-Cost Clock Deskew Buffer. DFT (2004)
Martin Omaña, Daniele Rossi, Cecilia Metra
Model for Transient Fault Susceptibility of Combinational Circuits. J. Electron. Test. 20 (5) (2004)
Martin Omaña, Daniele Rossi, Cecilia Metra
Novel Transient Fault Hardened Static Latch. ITC (2003)
Martin Omaña, Daniele Rossi, Cecilia Metra
High Speed and Highly Testable Parallel Two-Rail Code Checker. DATE (2003)
Cecilia Metra, T. M. Mak, Daniele Rossi
Clock Calibration Faults and their Impact on Quality of High Performance Microprocessors. DFT (2003)
Daniele Rossi, Cecilia Metra
Error Correcting Strategy for High Speed and High Density Reliable Flash Memories. J. Electron. Test. 19 (5) (2003)
L. Di Silvio, Daniele Rossi, Cecilia Metra
Crosstalk Effect Minimization for Encoded Busses. IOLTS (2003)
Daniele Rossi, Steven V. E. S. van Dijk, Richard P. Kleihorst, André K. Nieuwland, Cecilia Metra
Power Consumption of Fault Tolerant Codes: the Active Elements. IOLTS (2003)
Daniele Rossi, S. Cavallotti, Cecilia Metra
Error Correcting Codes for Crosstalk Effect Minimization. DFT (2003)
Martin Omaña, Giacinto Papasso, Daniele Rossi, Cecilia Metra
A Model for Transient Fault Propagation in Combinatorial Logic. IOLTS (2003)
Daniele Rossi, Cecilia Metra, Bruno Riccò
Fast and Compact Error Correcting Scheme for Reliable Multilevel Flash Memories. IOLTW (2002)
Daniele Rossi, Steven V. E. S. van Dijk, Richard P. Kleihorst, A. H. Nieuwland, Cecilia Metra
Coding Scheme for Low Energy Consumption Fault-Tolerant Bus. IOLTW (2002)
Daniele Rossi, Cecilia Metra, Bruno Riccò
Fast and Compact Error Correcting Scheme for Reliable Multilevel Flash Memories. MTDT (2002)