José Manuel Cazeaux

Publication Activity (10 Years)

Years Active: 2004-2014
Publications (10 Years): 0

Top Topics

Search Algorithm

Wireless Sensor Networks

Top Venues

J. Electron. Test.

Publications

Daniele Rossi, Martin Omaña, José Manuel Cazeaux, Cecilia Metra, T. M. Mak
Clock Faults Induced Min and Max Delay Violations. J. Electron. Test. 30 (1) (2014)
Daniele Rossi, José Manuel Cazeaux, Martin Omaña, Cecilia Metra, Abhijit Chatterjee
Accurate Linear Model for SET Critical Charge Estimation. IEEE Trans. Very Large Scale Integr. Syst. 17 (8) (2009)
Cecilia Metra, Martin Omaña, Daniele Rossi, José Manuel Cazeaux, T. M. Mak
Path (Min) Delay Faults and Their Impact on Self-Checking Circuits' Operation. IOLTS (2006)
Martin Omaña, José Manuel Cazeaux, Daniele Rossi, Cecilia Metra
Low-cost and highly reliable detector for transient and crosstalk faults affecting FPGA interconnects. DATE (2006)
Cecilia Metra, Daniele Rossi, Martin Omaña, José Manuel Cazeaux, T. M. Mak
Can Clock Faults be Detected Through Functional Test? DDECS (2006)
José Manuel Cazeaux, Daniele Rossi, Martin Omaña, Cecilia Metra, Abhijit Chatterjee
On Transistor Level Gate Sizing for Increased Robustness to Transient Faults. IOLTS (2005)
Cecilia Metra, Martin Omaña, Daniele Rossi, José Manuel Cazeaux, T. M. Mak
The Other Side of the Timing Equation: a Result of Clock Faults. DFT (2005)
José Manuel Cazeaux, Daniele Rossi, Cecilia Metra
Self-Checking Voter for High Speed TMR Systems. J. Electron. Test. 21 (4) (2005)
José Manuel Cazeaux, Martin Omaña, Cecilia Metra
Novel on-chip circuit for jitter testing in high-speed PLLs. IEEE Trans. Instrum. Meas. 54 (5) (2005)
José Manuel Cazeaux, Daniele Rossi, Cecilia Metra
New High Speed CMOS Self-Checking Voter. IOLTS (2004)
José Manuel Cazeaux, Martin Omaña, Cecilia Metra
Low-Area On-Chip Circuit for Jitter Measurement in a Phase-Locked Loop. IOLTS (2004)