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Novel on-chip circuit for jitter testing in high-speed PLLs.

José Manuel CazeauxMartin OmañaCecilia Metra
Published in: IEEE Trans. Instrum. Meas. (2005)
Keyphrases
  • high speed
  • low power
  • packet loss
  • real time
  • frame rate
  • test cases
  • high speed networks
  • test suite
  • software testing
  • circuit design
  • focal plane
  • shift register