Abhijit Jas

Publication Activity (10 Years)

Years Active: 1998-2013
Publications (10 Years): 0

Top Topics

Computer Architecture

Error Detection

Top Venues

J. Electron. Test.

Publications

Daniele Rossi, Martin Omaña, G. Garrammone, Cecilia Metra, Abhijit Jas, Rajesh Galivanche
Low Cost Concurrent Error Detection Strategy for the Control Logic of High Performance Microprocessors and Its Application to the Instruction Decoder. J. Electron. Test. 29 (3) (2013)
Hongxia Fang, Krishnendu Chakrabarty, Abhijit Jas, Srinivas Patil, Chandra Tirumurti
Functional Test-Sequence Grading at Register-Transfer Level. IEEE Trans. Very Large Scale Integr. Syst. 20 (10) (2012)
Michail Maniatakos, Naghmeh Karimi, Chandra Tirumurti, Abhijit Jas, Yiorgos Makris
Instruction-Level Impact Analysis of Low-Level Faults in a Modern Microprocessor Controller. IEEE Trans. Computers 60 (9) (2011)
Michail Maniatakos, Chandra Tirumurti, Abhijit Jas, Yiorgos Makris
AVF Analysis Acceleration via Hierarchical Fault Pruning. ETS (2011)
Naghmeh Karimi, Michail Maniatakos, Abhijit Jas, Chandra Tirumurti, Yiorgos Makris
Workload-Cognizant Concurrent Error Detection in the Scheduler of a Modern Microprocessor. IEEE Trans. Computers 60 (9) (2011)
Daniele Rossi, Martin Omaña, Gianluca Berghella, Cecilia Metra, Abhijit Jas, Chandra Tirumurti, Rajesh Galivanche
Low cost and low intrusive approach to test on-line the scheduler of high performance microprocessors. Conf. Computing Frontiers (2010)
Debasish Das, Kip Killpack, Chandramouli V. Kashyap, Abhijit Jas, Hai Zhou
Pessimism Reduction in Coupling-Aware Static Timing Analysis Using Timing and Logic Filtering. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (3) (2010)
Hongxia Fang, Krishnendu Chakrabarty, Abhijit Jas, Srinivas Patil, Chandra Tirumurti
RT-Level Deviation-Based Grading of Functional Test Sequences. VTS (2009)
Naghmeh Karimi, Michail Maniatakos, Chandra Tirumurti, Abhijit Jas, Yiorgos Makris
Impact analysis of performance faults in modern microprocessors. ICCD (2009)
Michail Maniatakos, Naghmeh Karimi, Chandra Tirumurti, Abhijit Jas, Yiorgos Makris
Instruction-Level Impact Comparison of RT- vs. Gate-Level Faults in a Modern Microprocessor Controller. VTS (2009)
Kanupriya Gulati, Suganth Paul, Sunil P. Khatri, Srinivas Patil, Abhijit Jas
FPGA-based hardware acceleration for Boolean satisfiability. ACM Trans. Design Autom. Electr. Syst. 14 (2) (2009)
Michail Maniatakos, Naghmeh Karimi, Yiorgos Makris, Abhijit Jas, Chandra Tirumurti
Design and Evaluation of a Timestamp-Based Concurrent Error Detection Method (CED) in a Modern Microprocessor Controller. DFT (2008)
Cecilia Metra, Daniele Rossi, Martin Omaña, Abhijit Jas, Rajesh Galivanche
Function-Inherent Code Checking: A New Low Cost On-Line Testing Approach for High Performance Microprocessor Control Logic. ETS (2008)
Debasish Das, Kip Killpack, Chandramouli V. Kashyap, Abhijit Jas, Hai Zhou
Pessimism reduction in coupling-aware static timing analysis using timing and logic filtering. ASP-DAC (2008)
Abhijit Jas, Yi-Shing Chang, Sreejit Chakravarty
A Methodology for Handling Complex Functional Constraints for Large Industrial Designs. J. Electron. Test. 24 (1-3) (2008)
Avijit Dutta, Abhijit Jas
Combinational Logic Circuit Protection Using Customized Error Detecting and Correcting Codes. ISQED (2008)
Naghmeh Karimi, Michail Maniatakos, Abhijit Jas, Yiorgos Makris
On the Correlation between Controller Faults and Instruction-Level Errors in Modern Microprocessors. ITC (2008)
Ramtilak Vemu, Abhijit Jas, Jacob A. Abraham, Srinivas Patil, Rajesh Galivanche
A low-cost concurrent error detection technique for processor control logic. DATE (2008)
Abhijit Jas, Suriyaprakash Natarajan, Srinivas Patil
The Region-Exhaustive Fault Model. ATS (2007)
Abhijit Jas, Srinivas Patil
Analysis of Specified Bit Handling Capability of Combinational Expander Networks. DFT (2007)
Abhijit Jas, Yi-Shing Chang, Sreejit Chakravarty
An Approach to Minimizing Functional Constraints. DFT (2006)
C. V. Krishna, Abhijit Jas, Nur A. Touba
Achieving high encoding efficiency with partial dynamic LFSR reseeding. ACM Trans. Design Autom. Electr. Syst. 9 (4) (2004)
Abhijit Jas, Bahram Pouya, Nur A. Touba
Test data compression technique for embedded cores using virtual scan chains. IEEE Trans. Very Large Scale Integr. Syst. 12 (7) (2004)
Abhijit Jas, C. V. Krishna, Nur A. Touba
Weighted pseudorandom hybrid BIST. IEEE Trans. Very Large Scale Integr. Syst. 12 (12) (2004)
Abhijit Jas, Jayabrata Ghosh-Dastidar, Mom-Eng Ng, Nur A. Touba
An efficient test vector compression scheme using selective Huffman coding. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22 (6) (2003)
Abhijit Jas, Nur A. Touba
Deterministic Test Vector Compression/Decompression for Systems-on-a-Chip Using an Embedded Processor. J. Electron. Test. 18 (4-5) (2002)
Abhijit Jas, C. V. Krishna, Nur A. Touba
Hybrid BIST Based on Weighted Pseudo-Random Testing: A New Test Resource Partitioning Scheme. VTS (2001)
C. V. Krishna, Abhijit Jas, Nur A. Touba
Test vector encoding using partial LFSR reseeding. ITC (2001)
Abhijit Jas, Bahram Pouya, Nur A. Touba
Virtual Scan Chains: A Means for Reducing Scan Length in Cores. VTS (2000)
Abhijit Jas, Kartik Mohanram, Nur A. Touba
An Embedded Core DFT Scheme to Obtain Highly Compressed Test Sets. Asian Test Symposium (1999)
Abhijit Jas, Jayabrata Ghosh-Dastidar, Nur A. Touba
Scan Vector Compression/Decompression Using Statistical Coding. VTS (1999)
Abhijit Jas, Nur A. Touba
Using an Embedded Processor for Efficient Deterministic Testing of Systems-on-a-Chip. ICCD (1999)
W. Quddus, Abhijit Jas, Nur A. Touba
Configuration self-test in FPGA-based reconfigurable systems. ISCAS (1) (1999)
Abhijit Jas, Nur A. Touba
Test vector decompression via cyclical scan chains and its application to testing core-based designs. ITC (1998)