Kartik Mohanram

Publication Activity (10 Years)

Years Active: 1999-2019
Publications (10 Years): 27

Top Topics

Image And Video Coding

Security Architecture

Authentication Scheme

Top Venues

ACM Great Lakes Symposium on VLSI

Publications

Shivam Swami, Kartik Mohanram
ASSET: Architectures for Smart Security of Non-Volatile Memories. ISVLSI (2019)
Joydeep Rakshit, Kartik Mohanram
LEO: Low Overhead Encryption ORAM for Non-Volatile Memories. IEEE Comput. Archit. Lett. 17 (2) (2018)
Shivam Swami, Joydeep Rakshit, Kartik Mohanram
STASH: security architecture for smart hybrid memories. DAC (2018)
Poovaiah M. Palangappa, Kartik Mohanram
RAPID: read acceleration for improved performance and endurance in MLC/TLC NVMs. ICCAD (2018)
Shivam Swami, Kartik Mohanram
ARSENAL: Architecture for Secure Non-Volatile Memories. IEEE Comput. Archit. Lett. 17 (2) (2018)
Ali Alsuwaiyan, Kartik Mohanram
MFNW: An MLC/TLC Flip-N-Write Architecture. ACM J. Emerg. Technol. Comput. Syst. 14 (2) (2018)
Joydeep Rakshit, Kartik Mohanram
ReadPRO: Read Prioritization Scheduling in ORAM for Efficient Obfuscation in Main Memories. ICCD (2018)
Shivam Swami, Kartik Mohanram
ACME: advanced counter mode encryption for secure non-volatile memories. DAC (2018)
Shivam Swami, Kartik Mohanram
ADAM: Architecture for write disturbance mitigation in scaled phase change memory. DATE (2018)
Poovaiah M. Palangappa, Kartik Mohanram
CASTLE: compression architecture for secure low latency, low energy, high endurance NVMs. DAC (2018)
Ali Alsuwaiyan, Kartik Mohanram
EP: Low latency, low energy program-and-verify for triple-level cell phase change memory. NANOARCH (2017)
Poovaiah M. Palangappa, Kartik Mohanram
CompEx++: Compression-Expansion Coding for Energy, Latency, and Lifetime Improvements in MLC/TLC NVMs. ACM Trans. Archit. Code Optim. 14 (1) (2017)
Shivam Swami, Poovaiah M. Palangappa, Kartik Mohanram
ECS: Error-Correcting Strings for Lifetime Improvements in Nonvolatile Memories. ACM Trans. Archit. Code Optim. 14 (4) (2017)
Joydeep Rakshit, Kartik Mohanram
ASSURE: Authentication Scheme for SecURE Energy Efficient Non-Volatile Memories. DAC (2017)
Jiayin Li, Kartik Mohanram
Virtual Two-Port Memory Architecture for Asymmetric Memory Technologies. VLSI Design (2017)
Shivam Swami, Kartik Mohanram
COVERT: Counter OVErflow ReducTion for efficient encryption of non-volatlle memories. DATE (2017)
Shivam Swami, Kartik Mohanram
Reliable Nonvolatile Memories: Techniques and Measures. IEEE Des. Test 34 (3) (2017)
Shivam Swami, Joydeep Rakshit, Kartik Mohanram
SECRET: smartly EnCRypted energy efficient non-volatile memories. DAC (2016)
Joydeep Rakshit, Kartik Mohanram, Runlai Wan, Kai Tak Lam, Jing Guo
Monolayer Transistor SRAMs: Toward Low-Power, Denser Memory Systems. ACM J. Emerg. Technol. Comput. Syst. 13 (2) (2016)
Shivam Swami, Kartik Mohanram
E3R: Energy Efficient Error Recovery for Multi/Triple-Level Cell Non-volatile Memories. VLSI Design (2016)
Poovaiah M. Palangappa, Kartik Mohanram
CompEx: Compression-expansion coding for energy, latency, and lifetime improvements in MLC/TLC NVM. HPCA (2016)
Poovaiah M. Palangappa, Jiayin Li, Kartik Mohanram
WOM-Code Solutions for Low Latency and High Endurance in Phase Change Memory. IEEE Trans. Computers 65 (4) (2016)
Ali Alsuwaiyan, Kartik Mohanram
An Offline Frequent Value Encoding for Energy-Efficient MLC/TLC Non-volatile Memories. ACM Great Lakes Symposium on VLSI (2016)
Poovaiah M. Palangappa, Kartik Mohanram
Flip-Mirror-Rotate: An Architecture for Bit-write Reduction and Wear Leveling in Non-volatile Memories. ACM Great Lakes Symposium on VLSI (2015)
Ali Alsuwaiyan, Kartik Mohanram
MFNW: A Flip-N-Write architecture for multi-level cell non-volatile memories. NANOARCH (2015)
Joydeep Rakshit, Runlai Wan, Kai Tak Lam, Jing Guo, Kartik Mohanram
Monolayer transition metal dichalcogenide and black phosphorus transistors for low power robust SRAM design. DAC (2015)
Jiayin Li, David B. Dgien, Nathan Altay Hunter, Yirong Zhao, Kartik Mohanram
Two-Port PCM Architecture for Network Processing. IEEE Trans. Very Large Scale Integr. Syst. 23 (10) (2015)
Jiayin Li, Kartik Mohanram
Write-once-memory-code phase change memory. DATE (2014)
David B. Dgien, Poovaiah M. Palangappa, Nathan Altay Hunter, Jiayin Li, Kartik Mohanram
Compression architecture for bit-write reduction in non-volatile memory technologies. NANOARCH (2014)
Mihir R. Choudhury, Vikas Chandra, Robert C. Aitken, Kartik Mohanram
Time-Borrowing Circuit Designs and Hardware Prototyping for Timing Error Resilience. IEEE Trans. Computers 63 (2) (2014)
Yirong Zhao, Jiayin Li, Kartik Mohanram
Multi-port FinFET SRAM design. ACM Great Lakes Symposium on VLSI (2013)
Kartik Mohanram, Matthew Wartell, Sundar Iyer
Mempack: an order of magnitude reduction in the cost, risk, and time for memory compiler certification. DATE (2013)
Mihir R. Choudhury, Kartik Mohanram
Low Cost Concurrent Error Masking Using Approximate Logic Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32 (8) (2013)
Kartik Mohanram, Xuebei Yang, Masoud Rostami, Guanxiong Liu, Alexander A. Balandin
Ambipolar circuits for analog, mixed-signal, and radio-frequency applications. NANOARCH (2012)
Kai Du, Peter J. Varman, Kartik Mohanram
High performance reliable variable latency carry select addition. DATE (2012)
Masoud Rostami, Kartik Mohanram
Independent-Gate FinFETs for Low Power Logic Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30 (3) (2011)
Andrew Zukoski, Mihir R. Choudhury, Kartik Mohanram
Reliability-driven don't care assignment for logic synthesis. DATE (2011)
Xuebei Yang, Kartik Mohanram
Robust 6T Si tunneling transistor SRAM design. DATE (2011)
Kai Du, Peter J. Varman, Kartik Mohanram
Static window addition: A new paradigm for the design of variable latency adders. ICCD (2011)
Andrew Zukoski, Xuebei Yang, Kartik Mohanram
Universal logic modules based on double-gate carbon nanotube transistors. DAC (2011)
M. Haykel Ben Jamaa, Kartik Mohanram, Giovanni De Micheli
An Efficient Gate Library for Ambipolar CNTFET Logic. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30 (2) (2011)
Xuebei Yang, Kartik Mohanram
Unequal-error-protection codes in SRAMs for mobile multimedia applications. ICCAD (2011)
Mihir R. Choudhury, Kartik Mohanram
Bi-decomposition of large Boolean functions using blocking edge graphs. ICCAD (2010)
Mihir R. Choudhury, Vikas Chandra, Kartik Mohanram, Robert C. Aitken
Analytical model for TDDB-based performance degradation in combinational logic. DATE (2010)
Xuebei Yang, Jyotsna Chauhan, Jing Guo, Kartik Mohanram
Graphene tunneling FET and its applications in low-power circuit design. ACM Great Lakes Symposium on VLSI (2010)
Xuebei Yang, Gianluca Fiori, Giuseppe Iannaccone, Kartik Mohanram
Semi-analytical model for schottky-barrier carbon nanotube and graphene nanoribbon transistors. ACM Great Lakes Symposium on VLSI (2010)
Mihir R. Choudhury, Masoud Rostami, Kartik Mohanram
Dominant critical gate identification for power and yield optimization in logic circuits. ACM Great Lakes Symposium on VLSI (2010)
Mihir R. Choudhury, Vikas Chandra, Kartik Mohanram, Robert C. Aitken
TIMBER: Time borrowing and error relaying for online timing error resilience. DATE (2010)
Masoud Rostami, Kartik Mohanram
independent-gate FinFET circuits. ASP-DAC (2010)
M. Haykel Ben Jamaa, Kartik Mohanram, Giovanni De Micheli
Power consumption of logic circuits in ambipolar carbon nanotube technology. DATE (2010)
Abhishek Garg, Kartik Mohanram, Alessandro Di Cara, Giovanni De Micheli, Ioannis Xenarios
Modeling stochasticity and robustness in gene regulatory networks. Bioinform. 25 (12) (2009)
Mihir R. Choudhury, Kartik Mohanram
Masking timing errors on speed-paths in logic circuits. DATE (2009)
Mihir R. Choudhury, Quming Zhou, Kartik Mohanram
Soft Error Rate Reduction Using Circuit Optimization and Transient Filter Insertion. J. Electron. Test. 25 (2-3) (2009)
Mihir R. Choudhury, Kartik Mohanram
Timing-driven optimization using lookahead logic circuits. DAC (2009)
M. Haykel Ben Jamaa, Kartik Mohanram, Giovanni De Micheli
Novel library of logic gates with ambipolar CNTFETs: Opportunities for multi-level logic synthesis. DATE (2009)
Mihir R. Choudhury, Kartik Mohanram
Reliability Analysis of Logic Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28 (3) (2009)
Mihir R. Choudhury, Youngki Yoon, Jing Guo, Kartik Mohanram
Technology exploration for graphene nanoribbon FETs. DAC (2008)
Kartik Mohanram
Error Detection and Tolerance for Scaled Electronic Technologies. DFT (2008)
Kartik Mohanram, Jing Guo
Graphene nanoribbon FETs: technology exploration and CAD. ICCAD (2008)
Quming Zhou, Mihir R. Choudhury, Kartik Mohanram
Tunable Transient Filters for Soft Error Rate Reduction in Combinational Circuits. ETS (2008)
Mihir R. Choudhury, Kartik Mohanram
Approximate logic circuits for low overhead, non-intrusive concurrent error detection. DATE (2008)
Kai Sun, Quming Zhou, Kartik Mohanram, Danny C. Sorensen
Parallel domain decomposition for simulation of large-scale power grids. ICCAD (2007)
Quming Zhou, Lin Zhong, Kartik Mohanram
Power signal processing: a new perspective for power analysis and optimization. ISLPED (2007)
Mosin Mondal, Kartik Mohanram, Yehia Massoud
Parameter-Variation-Aware Analysis for Noise Robustness. ISQED (2007)
Mihir R. Choudhury, Kartik Mohanram
Accurate and scalable reliability analysis of logic circuits. DATE (2007)
Mihir R. Choudhury, Kyle Ringgenberg, Scott Rixner, Kartik Mohanram
Interactive presentation: Single-ended coding techniques for off-chip interconnects to commodity memory. DATE (2007)
Alan L. Cox, Kartik Mohanram, Scott Rixner
Dependable != unaffordable. ASID (2006)
Quming Zhou, Mihir R. Choudhury, Kartik Mohanram
Design Optimization for Robustness to Single Event Upsets. VTS (2006)
Quming Zhou, Kartik Mohanram
Gate sizing to radiation harden combinational logic. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (1) (2006)
Mihir R. Choudhury, Quming Zhou, Kartik Mohanram
Design optimization for single-event upset robustness using simultaneous dual-VDD and sizing techniques. ICCAD (2006)
Quming Zhou, Kai Sun, Kartik Mohanram, Danny C. Sorensen
Large power grid analysis using domain decomposition. DATE (2006)
Quming Zhou, Kartik Mohanram
Elmore model for energy estimation in RC trees. DAC (2006)
Quming Zhou, Kartik Mohanram, Athanasios C. Antoulas
Structure preserving reduction of frequency-dependent interconnect. DAC (2005)
Kartik Mohanram
Closed-Form Simulation and Robustness Models for SEU-Tolerant Design. VTS (2005)
Kartik Mohanram
Simulation of transients caused by single-event upsets in combinational logic. ITC (2005)
Quming Zhou, Kartik Mohanram
Analysis of delay caused by bridging faults in RLC interconnects. ITC (2004)
Kartik Mohanram, Scott Rixner
Context-Independent Codes for Off-Chip Interconnects. PACS (2004)
Kartik Mohanram, Nur A. Touba
Lowering power consumption in concurrent checkers via input ordering. IEEE Trans. Very Large Scale Integr. Syst. 12 (11) (2004)
Quming Zhou, Kartik Mohanram
Cost-effective radiation hardening technique for combinational logic. ICCAD (2004)
Kartik Mohanram, Nur A. Touba
Eliminating Non-Determinism During Test of High-Speed Source Synchronous Differential Buses. VTS (2003)
Kartik Mohanram, Nur A. Touba
Cost-Effective Approach for Reducing Soft Error Failure Rate in Logic Circuits. ITC (2003)
Kartik Mohanram, Nur A. Touba
Partial Error Masking to Reduce Soft Error Failure Rate in Logic Circuits. DFT (2003)
Kartik Mohanram, Egor S. Sogomonyan, Michael Gössel, Nur A. Touba
Synthesis of Low-Cost Parity-Based Partially Self-Checking Circuits. IOLTS (2003)
Kartik Mohanram, C. V. Krishna, Nur A. Touba
A methodology for automated insertion of concurrent error detection hardware in synthesizable Verilog RTL. ISCAS (1) (2002)
Kartik Mohanram, Nur A. Touba
Input Ordering in Concurrent Checkers to Reduce Power Consumption. DFT (2002)
Abhijit Jas, Kartik Mohanram, Nur A. Touba
An Embedded Core DFT Scheme to Obtain Highly Compressed Test Sets. Asian Test Symposium (1999)