A methodology for automated insertion of concurrent error detection hardware in synthesizable Verilog RTL.
Kartik MohanramC. V. KrishnaNur A. ToubaPublished in: ISCAS (1) (2002)
Keyphrases
- error detection
- hardware description language
- integrated circuit
- error correction
- error recovery
- hardware design
- programmable logic
- hardware designs
- error correcting
- field programmable gate array
- data cleansing
- fault isolation
- fault tolerance
- error resilient
- embedded systems
- model based diagnosis
- fault tolerant
- real time
- low cost
- digital libraries
- neural network