Nur A. Touba

ORCID

Publication Activity (10 Years)

Years Active: 1994-2024
Publications (10 Years): 20

Top Venues

VTS

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

DFT

IEEE Trans. Computers

Publications

Abhishek Mishra, Mohammad Ershad Shaik, Anush Lingamoorthy, Suman Kumar, Anup Das, Nagarajan Kandasamy, Nur A. Touba
WaferCap: Open Classification of Wafer Map Patterns using Deep Capsule Network. VTS (2024)
Kenrick Xavier Pinto, Krishnaja Kodali, Abhishek Das, Nur A. Touba
Double Adjacent Error Correction in RRAM Matrix Multiplication using Weighted Checksums. IOLTS (2024)
Shruti Dutta, Sai Charan Rachamadugu Chinni, Abhishek Das, Nur A. Touba
Highly Efficient Layered Syndrome-based Double Error Correction Utilizing Current Summing in RRAM Cells to Simplify Decoder. DFT (2023)
Muhammad Imran, Taehyun Kwon, Nur A. Touba, Joon-Sung Yang
CEnT: An Efficient Architecture to Eliminate Intra-Array Write Disturbance in PCM. IEEE Trans. Computers 71 (5) (2022)
Abhishek Das, Nur A. Touba
Selective Checksum based On-line Error Correction for RRAM based Matrix Operations. VTS (2020)
Abhishek Das, Nur A. Touba
A New Class of Single Burst Error Correcting Codes with Parallel Decoding. IEEE Trans. Computers 69 (2) (2020)
Abhishek Das, Nur A. Touba
A Graph Theory Approach towards IJTAG Security via Controlled Scan Chain Isolation. VTS (2019)
Abhishek Das, Nur A. Touba
Online Correction of Hard Errors and Soft Errors via One-Step Decodable OLS Codes for Emerging Last Level Caches. LATS (2019)
Abhishek Das, Nur A. Touba
Layered-ECC: A Class of Double Error Correcting Codes for High Density Memory Systems. VTS (2019)
Abhishek Das, Nur A. Touba
Systematic b-adjacent symbol error correcting reed-solomon codes with parallel decoding. VTS (2018)
Abhishek Das, Nur A. Touba
Efficient Non-Binary Hamming Codes for Limited Magnitude Errors in MLC PCMs. DFT (2018)
Abhishek Das, Nur A. Touba
Low Complexity Burst Error Correcting Codes to Correct MBUs in SRAMs. ACM Great Lakes Symposium on VLSI (2018)
Taehee Lee, Nur A. Touba, Joon-Sung Yang
Enhancing Test Compression With Dependency Analysis for Multiple Expansion Ratios. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36 (9) (2017)
Abhishek Das, Nur A. Touba
Limited Magnitude Error Correction Using OLS Codes for Memories with Multilevel Cells. ICCD (2017)
Hyunseung Han, Nur A. Touba, Joon-Sung Yang
Exploiting Unused Spare Columns and Replaced Columns to Enhance Memory ECC. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36 (9) (2017)
Yu-Wei Lee, Nur A. Touba
Improving test compression with multiple-polynomial LFSRs. DFT (2017)
Yu-Wei Lee, Nur A. Touba
Computing with obfuscated data in arbitrary logic circuits via noise insertion and cancellation. DSC (2017)
Jin-Hyun Kang, Nur A. Touba, Joon-Sung Yang
Reducing control bit overhead for X-masking/X-canceling hybrid architecture via pattern partitioning. DAC (2016)
Joon-Sung Yang, Jinsuk Chung, Nur A. Touba
Enhancing Superset X-Canceling Method With Relaxed Constraints on Fault Observation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35 (2) (2016)
Kamran Saleem, Nur A. Touba
Using symbolic canceling to improve diagnosis from compacted response. ITC (2016)
Kamran Saleem, Sreenivaas S. Muthyala, Nur A. Touba
Compacting output responses containing unknowns using an embedded processor. DFTS (2015)
Yu-Wei Lee, Nur A. Touba
Improving logic obfuscation via logic cone analysis. LATS (2015)
Asad Amin Bawa, Nur A. Touba
Improving X-tolerant combinational output compaction via input rotation. DFTS (2015)
Muhammad Tauseef Rab, Asad Amin Bawa, Nur A. Touba
Reducing Cost of Yield Enhancement in 3-D Stacked Memories Via Asymmetric Layer Repair Capability. IEEE Trans. Very Large Scale Integr. Syst. 22 (9) (2014)
Sreenivaas S. Muthyala, Nur A. Touba
Improving test compression with scan feedforward techniques. ITC (2014)
Sreenivaas S. Muthyala, Nur A. Touba
Efficient Utilization of Test Elevators to Reduce Test Time in 3D-ICs. VLSI-SoC (Selected Papers) (2014)
Joon-Sung Yang, Jinkyu Lee, Nur A. Touba
Utilizing ATE Vector Repeat With Linear Decompressor for Test Vector Compression. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33 (8) (2014)
Sreenivaas S. Muthyala, Nur A. Touba
Reducing test time for 3D-ICs by improved utilization of test elevators. VLSI-SoC (2014)
Yu-Wei Lee, Nur A. Touba
Unified 3D test architecture for variable test data bandwidth across pre-bond, partial stack, and post-bond test. DFTS (2013)
Sreenivaas S. Muthyala, Nur A. Touba
SOC test compression scheme using sequential linear decompressors with retained free variables. VTS (2013)
Asad Amin Bawa, Muhammad Tauseef Rab, Nur A. Touba
Efficient compression of x-masking control data via dynamic channel allocation. DFTS (2013)
Pedro Reviriego, Shih-Fu Liu, Juan Antonio Maestro, S. Lee, Nur A. Touba, Rudrajit Datta
Implementing triple adjacent Error Correction in double error correction Orthogonal Latin Squares Codes. DFTS (2013)
Joon-Sung Yang, Nur A. Touba
Improved Trace Buffer Observation via Selective Data Capture Using 2-D Compaction for Post-Silicon Debug. IEEE Trans. Very Large Scale Integr. Syst. 21 (2) (2013)
Muhammad Tauseef Rab, Asad Amin Bawa, Nur A. Touba
Implementing defect tolerance in 3D-ICs by exploiting degrees of freedom in assembly. DFT (2012)
Joon-Sung Yang, Nur A. Touba
Efficient Trace Signal Selection for Silicon Debug by Error Transmission Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31 (3) (2012)
Muhammad Tauseef Rab, Asad Amin Bawa, Nur A. Touba
Using asymmetric layer repair capability to reduce the cost of yield enhancement in 3D stacked memories. VLSI-SoC (2012)
Joon-Sung Yang, Nur A. Touba, Benoit Nadeau-Dostie
Test Point Insertion with Control Points Driven by Existing Functional Flip-Flops. IEEE Trans. Computers 61 (10) (2012)
Asad Amin Bawa, Muhammad Tauseef Rab, Nur A. Touba
Using partial masking in X-chains to increase output compaction for an X-canceling MISR. DFT (2012)
Sreenivaas S. Muthyala, Nur A. Touba
Improving test compression by retaining non-pivot free variables in sequential linear decompressors. ITC (2012)
Jinsuk Chung, Nur A. Touba
Exploiting X-correlation in output compression via superset X-canceling. VTS (2012)
Joon-Sung Yang, Nur A. Touba
X-Canceling MISR Architectures for Output Response Compaction With Unknown Values. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31 (9) (2012)
Rudrajit Datta, Nur A. Touba
Designing a fast and adaptive error correction scheme for increasing the lifetime of phase change memories. VTS (2011)
Rudrajit Datta, Nur A. Touba
X-Stacking - A Method for Reducing Control Data for Output Compaction. DFT (2011)
Rudrajit Datta, Nur A. Touba
Generating Burst-Error Correcting Codes from Orthogonal Latin Square Codes - A Graph Theoretic Approach. DFT (2011)
Rudrajit Datta, Nur A. Touba
Post-manufacturing ECC customization based on Orthogonal Latin Square codes and its application to ultra-low power caches. ITC (2010)
Shianling Wu, Laung-Terng Wang, Lizhen Yu, Hiroshi Furukawa, Xiaoqing Wen, Wen-Ben Jone, Nur A. Touba, FeiFei Zhao, Jinsong Liu, Hao-Jan Chao, Fangfang Li, Zhigang Jiang
Logic BIST Architecture Using Staggered Launch-on-Shift for Testing Designs Containing Asynchronous Clock Domains. DFT (2010)
Jinkyu Lee, Nur A. Touba
Correlation-Based Rectangular Encoding. IEEE Trans. Very Large Scale Integr. Syst. 18 (10) (2010)
Laung-Terng Wang, Nur A. Touba, Zhigang Jiang, Shianling Wu, Jiun-Lang Huang, James Chien-Mo Li
CSER: BISER-based concurrent soft-error resilience. VTS (2010)
Joon-Sung Yang, Benoit Nadeau-Dostie, Nur A. Touba
Test point insertion using functional flip-flops to drive control points. ITC (2009)
Joon-Sung Yang, Nur A. Touba, Shih-Yu Yang, T. M. Mak
An industrial case study for X-canceling MISR. ITC (2009)
Rudrajit Datta, Nur A. Touba
Exploiting Unused Spare Columns to Improve Memory ECC. VTS (2009)
Joon-Sung Yang, Benoit Nadeau-Dostie, Nur A. Touba
Reducing Test Point Area for BIST through Greater Use of Functional Flip-Flops to Drive Control Points. DFT (2009)
Joon-Sung Yang, Nur A. Touba
Automated Selection of Signals to Observe for Efficient Silicon Debug. VTS (2009)
Muhammad Tauseef Rab, Asad Amin Bawa, Nur A. Touba
Improving Memory Repair by Selective Row Partitioning. DFT (2009)
Joon-Sung Yang, Nur A. Touba
Enhancing Silicon Debug via Periodic Monitoring. DFT (2008)
Joon-Sung Yang, Nur A. Touba
Expanding Trace Buffer Observation Window for In-System Silicon Debug through Selective Capture. VTS (2008)
Scott Davidson, Nur A. Touba
Guest Editors' Introduction: Progress in Test Compression. IEEE Des. Test Comput. 25 (2) (2008)
Nur A. Touba
ITC 2008 Highlights. IEEE Des. Test Comput. 25 (5) (2008)
Nur A. Touba, Adelio Salsano, Minsu Choi
Guest Editorial. J. Electron. Test. 24 (1-3) (2008)
Ritesh Garg, Richard Putman, Nur A. Touba
Increasing Output Compaction in Presence of Unknowns Using an X-Canceling MISR with Deterministic Observation. VTS (2008)
Avijit Dutta, Nur A. Touba
Multiple Bit Upset Tolerant Memory Using a Selective Cycle Avoidance Based SEC-DED-DAEC Code. VTS (2007)
Avijit Dutta, Nur A. Touba
Reliable Network-on-Chip Using a Low Cost Unequal Error Protection Code. DFT (2007)
Richard Putman, Nur A. Touba
Using Multiple Expansion Ratios and Dependency Analysis to Improve Test Compression. VTS (2007)
Nur A. Touba
X-canceling MISR - An X-tolerant methodology for compacting output responses with unknowns using a MISR. ITC (2007)
Jinkyu Lee, Nur A. Touba
LFSR-Reseeding Scheme Achieving Low-Power Dissipation During Test. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (2) (2007)
Kedarnath J. Balakrishnan, Nur A. Touba
Relationship Between Entropy and Test Data Compression. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (2) (2007)
Avijit Dutta, Nur A. Touba
Iterative OPDD Based Signal Probability Calculation. VTS (2006)
Avijit Dutta, Nur A. Touba
Using Limited Dependence Sequential Expansion for Decompressing Test Vectors. ITC (2006)
Nur A. Touba
Survey of Test Vector Compression Techniques. IEEE Des. Test Comput. 23 (4) (2006)
Jinkyu Lee, Nur A. Touba
Combining Linear and Non-Linear Test Vector Compression Using Correlation-Based Rectangular Encoding. VTS (2006)
Avijit Dutta, Nur A. Touba
Synthesis of Efficient Linear Test Pattern Generators. DFT (2006)
Jinkyu Lee, Nur A. Touba
Efficiently Utilizing ATE Vector Repeat for Compression by Scan Vector Decomposition. ATS (2006)
Eric MacDonald, Nur A. Touba
Delay testing of partially depleted silicon-on-insulator (PD-SOI) circuits. IEEE Trans. Very Large Scale Integr. Syst. 14 (6) (2006)
Kedarnath J. Balakrishnan, Nur A. Touba
Improving Linear Test Data Compression. IEEE Trans. Very Large Scale Integr. Syst. 14 (11) (2006)
Shalini Ghosh, Sugato Basu, Nur A. Touba
Selecting Error Correcting Codes to Minimize Power in Memory Checker Circuits. J. Low Power Electron. 1 (1) (2005)
Avijit Dutta, Terence Rodrigues, Nur A. Touba
Low Cost Test Vector Compression/Decompression Scheme for Circuits with a Reconfigurable Serial Multiplier. ISVLSI (2005)
Nur A. Touba
Methods for improving test compression. ITC (2005)
Kedarnath J. Balakrishnan, Nur A. Touba
Reconfigurable Linear Decompressors Using Symbolic Gaussian Elimination. DATE (2005)
Avijit Dutta, Nur A. Touba
Synthesis of nonintrusive concurrent error detection using an even error detecting function. ITC (2005)
Kedarnath J. Balakrishnan, Nur A. Touba, Srinivas Patil
Compressing Functional Tests for Microprocessors. Asian Test Symposium (2005)
Samuel I. Ward, Chris Schattauer, Nur A. Touba
Using Statistical Transformations to Improve Compression for Linear Decompressors. DFT (2005)
Shalini Ghosh, Sugato Basu, Nur A. Touba
Synthesis of Low Power CED Circuits Based on Parity Codes. VTS (2005)
Jinkyu Lee, Nur A. Touba
Low Power BIST Based on Scan Partitioning. DFT (2005)
C. V. Krishna, Abhijit Jas, Nur A. Touba
Achieving high encoding efficiency with partial dynamic LFSR reseeding. ACM Trans. Design Autom. Electr. Syst. 9 (4) (2004)
Kedarnath J. Balakrishnan, Nur A. Touba
Improving Encoding Efficiency for Linear Decompressors Using Scan Inversion. ITC (2004)
Abhijit Jas, Bahram Pouya, Nur A. Touba
Test data compression technique for embedded cores using virtual scan chains. IEEE Trans. Very Large Scale Integr. Syst. 12 (7) (2004)
Jinkyu Lee, Nur A. Touba
Low Power Test Data Compression Based on LFSR Reseeding. ICCD (2004)
Kedarnath J. Balakrishnan, Nur A. Touba
Relating entropy theory to test data compression. ETS (2004)
Kedarnath J. Balakrishnan, Nur A. Touba
Matrix-based software test data decompression for systems-on-a-chip. J. Syst. Archit. 50 (5) (2004)
Abhijit Jas, C. V. Krishna, Nur A. Touba
Weighted pseudorandom hybrid BIST. IEEE Trans. Very Large Scale Integr. Syst. 12 (12) (2004)
Shalini Ghosh, Eric MacDonald, Sugato Basu, Nur A. Touba
Low-power weighted pseudo-random BIST using special scan cells. ACM Great Lakes Symposium on VLSI (2004)
Shalini Ghosh, Nur A. Touba, Sugato Basu
Reducing Power Consumption in Memory ECC Checkers. ITC (2004)
C. V. Krishna, Nur A. Touba
3-Stage Variable Length Continuous-Flow Scan Vector Decompression Scheme. VTS (2004)
Kartik Mohanram, Nur A. Touba
Lowering power consumption in concurrent checkers via input ordering. IEEE Trans. Very Large Scale Integr. Syst. 12 (11) (2004)
Kedarnath J. Balakrishnan, Nur A. Touba
Deterministic Test Vector Decompression in Software Using Linear Operations. VTS (2003)
Kartik Mohanram, Nur A. Touba
Eliminating Non-Determinism During Test of High-Speed Source Synchronous Differential Buses. VTS (2003)
Kartik Mohanram, Nur A. Touba
Cost-Effective Approach for Reducing Soft Error Failure Rate in Logic Circuits. ITC (2003)
Kedarnath J. Balakrishnan, Nur A. Touba
Scan-Based BIST Diagnosis Using an Embedded Processor. DFT (2003)
Lei Li, Krishnendu Chakrabarty, Nur A. Touba
Test data compression using dictionaries with selective entries and fixed-length indices. ACM Trans. Design Autom. Electr. Syst. 8 (4) (2003)
Kartik Mohanram, Nur A. Touba
Partial Error Masking to Reduce Soft Error Failure Rate in Logic Circuits. DFT (2003)

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Publication Activity (10 Years)

Top Topics

Top Venues

Nur A. Touba