Synthesis of Low Power CED Circuits Based on Parity Codes.
Shalini GhoshSugato BasuNur A. ToubaPublished in: VTS (2005)
Keyphrases
- low power
- logic circuits
- high speed
- error correction
- logic synthesis
- power consumption
- cmos technology
- power dissipation
- power reduction
- vlsi circuits
- delay insensitive
- low cost
- mixed signal
- analog circuits
- single chip
- high power
- low power consumption
- digital signal processing
- wireless transmission
- vlsi architecture
- gate array
- low voltage
- image sensor
- data hiding
- low density parity check
- real time
- channel coding