Srinivas Patil

Publication Activity (10 Years)

Years Active: 1989-2012
Publications (10 Years): 0

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Naghmeh Karimi, Krishnendu Chakrabarty, Pallav Gupta, Srinivas Patil
Test generation for clock-domain crossing faults in integrated circuits. DATE (2012)
Hongxia Fang, Krishnendu Chakrabarty, Abhijit Jas, Srinivas Patil, Chandra Tirumurti
Functional Test-Sequence Grading at Register-Transfer Level. IEEE Trans. Very Large Scale Integr. Syst. 20 (10) (2012)
Naghmeh Karimi, Zhiqiu Kong, Krishnendu Chakrabarty, Pallav Gupta, Srinivas Patil
Testing of Clock-Domain Crossing Faults in Multi-core System-on-Chip. Asian Test Symposium (2011)
Hongxia Fang, Krishnendu Chakrabarty, Abhijit Jas, Srinivas Patil, Chandra Tirumurti
RT-Level Deviation-Based Grading of Functional Test Sequences. VTS (2009)
Gadi Singer, Rajesh Galivanche, Srinivas Patil, Mike Tripp
The Challenges of Nanotechnology and Gigacomplexity. IEEE Des. Test Comput. 26 (1) (2009)
Kanupriya Gulati, Suganth Paul, Sunil P. Khatri, Srinivas Patil, Abhijit Jas
FPGA-based hardware acceleration for Boolean satisfiability. ACM Trans. Design Autom. Electr. Syst. 14 (2) (2009)
Ramtilak Vemu, Abhijit Jas, Jacob A. Abraham, Srinivas Patil, Rajesh Galivanche
A low-cost concurrent error detection technique for processor control logic. DATE (2008)
Abhijit Jas, Suriyaprakash Natarajan, Srinivas Patil
The Region-Exhaustive Fault Model. ATS (2007)
Irith Pomeranz, Praveen Parvathala, Srinivas Patil
Estimating the Fault Coverage of Functional Test Sequences Without Fault Simulation. ATS (2007)
Abhijit Jas, Srinivas Patil
Analysis of Specified Bit Handling Capability of Combinational Expander Networks. DFT (2007)
Irith Pomeranz, Srinivas Patil, Praveen Parvathala
A Functional Fault Model with Implicit Fault Effect Propagation Requirements. ATS (2006)
Sungchul Park, Li Chen, Praveen Parvathala, Srinivas Patil, Irith Pomeranz
A Functional Coverage Metric for Estimating the Gate-Level Fault Coverage of Functional Tests. ITC (2006)
Hangkyu Lee, Suriyaprakash Natarajan, Srinivas Patil, Irith Pomeranz
Selecting High-Quality Delay Tests for Manufacturing Test and Debug. DFT (2006)
Suriyaprakash Natarajan, Srinivas Patil, Sreejit Chakravarty
Path Delay Fault Simulation on Large Industrial Designs. VTS (2006)
Kedarnath J. Balakrishnan, Nur A. Touba, Srinivas Patil
Compressing Functional Tests for Microprocessors. Asian Test Symposium (2005)
Rohit Kapur, Srinivas Patil, Thomas J. Snethen, Thomas W. Williams
A weighted random pattern test generation system. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15 (8) (1996)
Jacob Savir, Srinivas Patil
Broad-side delay test. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13 (8) (1994)
Rohit Kapur, Srinivas Patil, Thomas J. Snethen, Thomas W. Williams
Design of an Efficient Weighted-Random-Pattern Generation System. ITC (1994)
Jacob Savir, Srinivas Patil
On broad-side delay test. VTS (1994)
Jacob Savir, Srinivas Patil
On broad-side delay test. IEEE Trans. Very Large Scale Integr. Syst. 2 (3) (1994)
Jacob Savir, Srinivas Patil
Scan-based transition test. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12 (8) (1993)
Srinivas Patil, Jacob Savir
Skewed-Load Transition Test: Part 2, Coverage. ITC (1992)
Sungho Kim, Prithviraj Banerjee, Srinivas Patil
A Layout Driven Design for Testability Technique for MOS VLSI Circuits. ITC (1991)
Srinivas Patil, Prithviraj Banerjee, Janak H. Patel
Parallel Test Generation for Sequential Circuits on General-Purpose Multiprocessors. DAC (1991)
Srinivas Patil, Prithviraj Banerjee
Performance trade-offs in a parallel test generation/fault simulation environment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10 (12) (1991)
Srinivas Patil, Prithviraj Banerjee
A parallel branch and bound algorithm for test generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9 (3) (1990)
Srinivas Patil, Prithviraj Banerjee
Fault Partitioning Issues in an Integrated Parallel Test Generation/Fault Simulation Environment. ITC (1989)
Srinivas Patil, Prithviraj Banerjee, Constantine D. Polychronopoulos
Efficient circuit partitioning algorithms for parallel logic simulation. SC (1989)
Srinivas Patil, Prithviraj Banerjee
A Parallel Branch and Bound Algorithm for Test Generation. DAC (1989)
Srinivas Patil, Sudhakar M. Reddy
A test generation system for path delay faults. ICCD (1989)