Pallav Gupta

Publication Activity (10 Years)

Years Active: 2003-2018
Publications (10 Years): 2

Top Topics

Fault Diagnosis

Carbon Nanotubes

Physical Design

Schottky Barrier

Top Venues

ACM J. Emerg. Technol. Comput. Syst.

ACM Trans. Embed. Comput. Syst.

Publications

Pallav Gupta
An Effective Methodology for Automated Diagnosis of Functional Pattern Failures to Support Silicon Debug. ITC (2018)
I-De Huang, Pallav Gupta, Loganathan Lingappan, Vijay Gangaram
Online Scan Diagnosis : A Novel Approach to Volume Diagnosis. ITC (2018)
Hao Liang, Wei Zhang, Jiale Huang, Shengqi Yang, Pallav Gupta
Leveraging Hotspots and Improving Chip Reliability via Carbon Nanotube Grid Thermal Structure. IEEE Trans. Very Large Scale Integr. Syst. 23 (4) (2015)
Shengqi Yang, Wenping Wang, Mark Hagan, Wei Zhang, Pallav Gupta, Yu Cao
NBTI-aware circuit node criticality computation. ACM J. Emerg. Technol. Comput. Syst. 9 (3) (2013)
Naghmeh Karimi, Krishnendu Chakrabarty, Pallav Gupta, Srinivas Patil
Test generation for clock-domain crossing faults in integrated circuits. DATE (2012)
Shengqi Yang, Pallav Gupta, Marilyn Wolf, Dimitrios N. Serpanos, Vijaykrishnan Narayanan, Yuan Xie
Power Analysis Attack Resistance Engineering by Dynamic Voltage and Frequency Scaling. ACM Trans. Embed. Comput. Syst. 11 (3) (2012)
Jiale Huang, Minhao Zhu, Shengqi Yang, Pallav Gupta, Wei Zhang, Steven M. Rubin, Gilda Garretón, Jin He
A physical design tool for carbon nanotube field-effect transistor circuits. ACM J. Emerg. Technol. Comput. Syst. 8 (3) (2012)
Wei Zhang, Jiale Huang, Shengqi Yang, Pallav Gupta
Case study: Alleviating hotspots and improving chip reliability via carbon nanotube thermal interface. DATE (2011)
Naghmeh Karimi, Zhiqiu Kong, Krishnendu Chakrabarty, Pallav Gupta, Srinivas Patil
Testing of Clock-Domain Crossing Faults in Multi-core System-on-Chip. Asian Test Symposium (2011)
Xiaofang (Maggie) Wang, Pallav Gupta
Resource-constrained multiprocessor synthesis for floating-point applications on FPGAs. ACM Trans. Design Autom. Electr. Syst. 16 (4) (2011)
Pallav Gupta, Rui Zhang, Niraj K. Jha
Automatic Test Generation for Combinational Threshold Logic Networks. IEEE Trans. Very Large Scale Integr. Syst. 16 (8) (2008)
Pallav Gupta, Niraj K. Jha, Loganathan Lingappan
A Test Generation Framework for Quantum Cellular Automata Circuits. IEEE Trans. Very Large Scale Integr. Syst. 15 (1) (2007)
Rui Zhang, Pallav Gupta, Niraj K. Jha
Majority and Minority Network Synthesis With Application to QCA-, SET-, and TPL-Based Nanotechnologies. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (7) (2007)
Pallav Gupta, Abhinav Agrawal, Niraj K. Jha
An Algorithm for Synthesis of Reversible Logic Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (11) (2006)
Pallav Gupta, Niraj K. Jha, Loganathan Lingappan
Test generation for combinational quantum cellular automata (QCA) circuits. DATE (2006)
Pallav Gupta, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
Efficient fingerprint-based user authentication for embedded systems. DAC (2005)
Rui Zhang, Pallav Gupta, Lin Zhong, Niraj K. Jha
Threshold network synthesis and optimization and its application to nanotechnologies. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24 (1) (2005)
Rui Zhang, Pallav Gupta, Niraj K. Jha
Synthesis of Majority and Minority Networks and Its Applications to QCA, TPL and SET Based Nanotechnologies. VLSI Design (2005)
Pallav Gupta, Niraj K. Jha
An Algorithm for Nano-Pipelining of Circuits and Architectures for a Nanotechnology. DATE (2004)
Rui Zhang, Pallav Gupta, Lin Zhong, Niraj K. Jha
Synthesis and Optimization of Threshold Logic Networks with Application to Nanotechnologies. DATE (2004)
Pallav Gupta, Rui Zhang, Niraj K. Jha
An Automatic Test Pattern Generation Framework for Combinational Threshold Logic Networks. ICCD (2004)
Pallav Gupta, Lin Zhong, Niraj K. Jha
A High-level Interconnect Power Model for Design Space Exploration. ICCAD (2003)