Loganathan Lingappan

Publication Activity (10 Years)

Years Active: 2003-2018
Publications (10 Years): 4

Top Topics

Modulo Theories

Statistical Tests

Diagnostic Tests

Top Venues

Publications

Sarmad Tanwir, Michael S. Hsiao, Loganathan Lingappan
An online framework for diagnosis of multiple defects in scan chains. ISQED (2018)
I-De Huang, Pallav Gupta, Loganathan Lingappan, Vijay Gangaram
Online Scan Diagnosis : A Novel Approach to Volume Diagnosis. ITC (2018)
Sarmad Tanwir, Michael S. Hsiao, Loganathan Lingappan
A Test Pattern Quality Metric for Diagnosis of Multiple Stuck-at and Transition faults. ACM Great Lakes Symposium on VLSI (2017)
Sarmad Tanwir, Michael S. Hsiao, Loganathan Lingappan
Hardware-in-the-loop model-less diagnostic test generation. HLDVT (2016)
Sarmad Tanwir, Sarvesh Prabhu, Michael S. Hsiao, Loganathan Lingappan
Information-theoretic and statistical methods of failure log selection for improved diagnosis. ITC (2015)
Sarvesh Prabhu, Michael S. Hsiao, Loganathan Lingappan, Vijay Gangaram
Test generation for circuits with embedded memories using SMT. ETS (2013)
Sarvesh Prabhu, Michael S. Hsiao, Loganathan Lingappan, Vijay Gangaram
A Novel SMT-Based Technique for LFSR Reseeding. VLSI Design (2012)
Sarvesh Prabhu, Michael S. Hsiao, Loganathan Lingappan, Vijay Gangaram
A SMT-based diagnostic test generation method for combinational circuits. VTS (2012)
Saparya Krishnamoorthy, Michael S. Hsiao, Loganathan Lingappan
Strategies for scalable symbolic execution-driven test generation for programs. Sci. China Inf. Sci. 54 (9) (2011)
Sarvesh Prabhu, Michael S. Hsiao, Saparya Krishnamoorthy, Loganathan Lingappan, Vijay Gangaram, Jim Grundy
An Efficient 2-Phase Strategy to Achieve High Branch Coverage. Asian Test Symposium (2011)
Saparya Krishnamoorthy, Michael S. Hsiao, Loganathan Lingappan
Tackling the Path Explosion Problem in Symbolic Execution-Driven Test Generation for Programs. Asian Test Symposium (2010)
Loganathan Lingappan, Vijay Gangaram, Niraj K. Jha, Sreejit Chakravarty
Fast Enhancement of Validation Test Sets for Improving the Stuck-at Fault Coverage of RTL Circuits. IEEE Trans. Very Large Scale Integr. Syst. 17 (5) (2009)
Pallav Gupta, Niraj K. Jha, Loganathan Lingappan
A Test Generation Framework for Quantum Cellular Automata Circuits. IEEE Trans. Very Large Scale Integr. Syst. 15 (1) (2007)
Loganathan Lingappan, Vijay Gangaram, Niraj K. Jha
Fast Enhancement of Validation Test Sets to Improve Stuck-at Fault Coverage for RTL circuits. VLSI Design (2007)
Loganathan Lingappan, Niraj K. Jha
Satisfiability-Based Automatic Test Program Generation and Design for Testability for Microprocessors. IEEE Trans. Very Large Scale Integr. Syst. 15 (5) (2007)
Loganathan Lingappan, Niraj K. Jha
Efficient Design for Testability Solution Based on Unsatisfiability for Register-Transfer Level Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (7) (2007)
Loganathan Lingappan, Srivaths Ravi, Niraj K. Jha
Satisfiability-based test generation for nonseparable RTL controller-datapath circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (3) (2006)
Loganathan Lingappan, Niraj K. Jha
Improving the Performance of Automatic Sequential Test Generation by Targeting Hard-to-Test Faults. VLSI Design (2006)
Loganathan Lingappan, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha, Srimat T. Chakradhar
Test-Volume Reduction in Systems-on-a-Chip Using Heterogeneous and Multilevel Compression Techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (10) (2006)
Pallav Gupta, Niraj K. Jha, Loganathan Lingappan
Test generation for combinational quantum cellular automata (QCA) circuits. DATE (2006)
Loganathan Lingappan, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha, Srimat T. Chakradhar
Heterogeneous and Multi-Level Compression Techniques for Test Volume Reduction in Systems-on-Chip. VLSI Design (2005)
Loganathan Lingappan, Niraj K. Jha
Unsatisfiability Based Efficient Design for Testability Solution for Register-Transfer Level Circuits. VTS (2005)
Loganathan Lingappan, Srivaths Ravi, Niraj K. Jha
Test Generation for Non-separable RTL Controller-datapath Circuits using a Satisfiability based Approach. ICCD (2003)