Thomas J. Snethen

Publication Activity (10 Years)

Years Active: 1970-2014
Publications (10 Years): 0

Top Topics

Highly Efficient

Hierarchical Structure

Top Venues

Publications

Brion L. Keller, Krishna Chakravadhanula, Brian Foutz, Vivek Chickermane, Akhil Garg, Richard Schoonover, James Sage, Don Pearl, Thomas J. Snethen
Efficient testing of hierarchical core-based SOCs. ITC (2014)
Brion L. Keller, Krishna Chakravadhanula, Brian Foutz, Vivek Chickermane, R. Malneedi, Thomas J. Snethen, Vikram Iyengar, David E. Lackey, Gary Grise
Low cost at-speed testing using On-Product Clock Generation compatible with test compression. ITC (2010)
Anis Uzzaman, Brion L. Keller, Thomas J. Snethen, Kazuhiko Iwasaki, Masayuki Arai
Automatic Handling of Programmable On-Product Clock Generation (OPCG) Circuitry for Low Power Aware Delay Test. J. Low Power Electron. 5 (4) (2009)
Brion L. Keller, Anis Uzzaman, Bibo Li, Thomas J. Snethen
Using Programmable On-Product Clock Generation (OPCG) for Delay Test. ATS (2007)
Anis Uzzaman, Bibo Li, Thomas J. Snethen, Brion L. Keller, Gary Grise
Automated handling of programmable on-product clock generation (OPCG) circuitry for delay test vector generation. ITC (2007)
Bernd Könemann, Carl Barnhart, Brion L. Keller, Thomas J. Snethen, Owen Farnsworth, Donald L. Wheater
A SmartBIST Variant with Guaranteed Encoding. Asian Test Symposium (2001)
Xinghao Chen, Thomas J. Snethen, Joe Swenton, Ron Walther
A Simplified Method for Testing the IBM Pipeline Partial-Scan Microprocessor. Asian Test Symposium (1999)
Mary P. Kusko, Bryan J. Robbins, Thomas J. Snethen, Peilin Song, Thomas G. Foote, William V. Huott
Microprocessor test and test tool methodology for the 500 MHz IBM S/390 G5 chip. ITC (1998)
William V. Huott, Timothy J. Koprowski, Bryan J. Robbins, Mary P. Kusko, Stephen Pateras, Dale E. Hoffman, Timothy G. McNamara, Thomas J. Snethen
Advanced microprocessor test strategy and methodology. IBM J. Res. Dev. 41 (4&5) (1997)
Rohit Kapur, Srinivas Patil, Thomas J. Snethen, Thomas W. Williams
A weighted random pattern test generation system. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15 (8) (1996)
Rohit Kapur, Srinivas Patil, Thomas J. Snethen, Thomas W. Williams
Design of an Efficient Weighted-Random-Pattern Generation System. ITC (1994)
Thomas J. Snethen
Simulator-oriented fault test generator. DAC (1977)
Manuel Correia, Donald Cossman, Franco Putzolu, Thomas J. Snethen
Minimizing the problem of logic testing by the interaction of a design group with user-oriented facilities. DAC (1970)