David E. Lackey

Publication Activity (10 Years)

Years Active: 1996-2010
Publications (10 Years): 0

Publications

Brion L. Keller, Krishna Chakravadhanula, Brian Foutz, Vivek Chickermane, R. Malneedi, Thomas J. Snethen, Vikram Iyengar, David E. Lackey, Gary Grise
Low cost at-speed testing using On-Product Clock Generation compatible with test compression. ITC (2010)
Vikram Iyengar, Kenneth Pichamuthu, Andrew Ferko, Frank Woytowich, David E. Lackey, Gary Grise, Mark Taylor, Mike Degregorio, Steven F. Oakland
An Integrated Framework for At-Speed and ATE-Driven Delay Test of Contract-Manufactured ASICs. VTS (2007)
Vikram Iyengar, Jinjun Xiong, Subbayyan Venkatesan, Vladimir Zolotov, David E. Lackey, Peter A. Habitz, Chandu Visweswariah
Variation-aware performance verification using at-speed structural test and statistical timing. ICCAD (2007)
David E. Lackey
Efficient Latch and Clock Structures for System-on-Chip Test Flexibility. ITC (2006)
Jürgen Koehl, David E. Lackey, George W. Doerre
IBM's 50 Million gate ASICs. ASP-DAC (2003)
David E. Lackey, Paul S. Zuchowski, Jürgen Koehl
Designing mega-ASICs in nanogate technologies. DAC (2003)
David E. Lackey, Paul S. Zuchowski, Thomas R. Bednar, Douglas W. Stout, Scott W. Gould, John M. Cohn
Managing power and performance for System-on-Chip designs using Voltage Islands. ICCAD (2002)
George W. Doerre, David E. Lackey
The IBM ASIC/SoC methodology - A recipe for first-time success. IBM J. Res. Dev. 46 (6) (2002)
David E. Lackey
Applying placement-based synthesis for on-time system-on-a-chip design. CICC (2000)
James J. Engel, Thomas S. Guzowski, Anderson Hunt, David E. Lackey, Lansing D. Pickup, Robert A. Proctor, Karla Reynolds, Ann Marie Rincon, David R. Stauffer
Design methodology for IBM ASIC products. IBM J. Res. Dev. 40 (4) (1996)