Brion L. Keller

Publication Activity (10 Years)

Years Active: 1991-2015
Publications (10 Years): 0

Top Topics

Computationally Expensive

Top Venues

Publications

Konstantin Shibin, Vivek Chickermane, Brion L. Keller, Christos Papameletis, Erik Jan Marinissen
At-Speed Testing of Inter-Die Connections of 3D-SICs in the Presence of Shore Logic. ATS (2015)
Christos Papameletis, Brion L. Keller, Vivek Chickermane, Said Hamdioui, Erik Jan Marinissen
A DfT Architecture and Tool Flow for 3-D SICs With Test Data Compression, Embedded Cores, and Multiple Towers. IEEE Des. Test 32 (4) (2015)
Brion L. Keller, Krishna Chakravadhanula, Brian Foutz, Vivek Chickermane, Akhil Garg, Richard Schoonover, James Sage, Don Pearl, Thomas J. Snethen
Efficient testing of hierarchical core-based SOCs. ITC (2014)
Sandeep Kumar Goel, Saman Adham, Min-Jer Wang, Ji-Jan Chen, Tze-Chiang Huang, Ashok Mehta, Frank Lee, Vivek Chickermane, Brion L. Keller, Thomas Valind, Subhasish Mukherjee, Navdeep Sood, Jeongho Cho, Hayden Hyungdong Lee, Jungi Choi, Sangdoo Kim
Test and debug strategy for TSMC CoWoS™ stacking process based heterogeneous 3D IC: A silicon case study. ITC (2013)
Christos Papameletis, Brion L. Keller, Vivek Chickermane, Erik Jan Marinissen, Said Hamdioui
Automated DfT insertion and test generation for 3D-SICs with embedded cores and multiple towers. ETS (2013)
Sergej Deutsch, Brion L. Keller, Vivek Chickermane, Subhasish Mukherjee, Navdeep Sood, Sandeep Kumar Goel, Ji-Jan Chen, Ashok Mehta, Frank Lee, Erik Jan Marinissen
DfT architecture and ATPG for Interconnect tests of JEDEC Wide-I/O memory-on-logic die stacks. ITC (2012)
Sergej Deutsch, Vivek Chickermane, Brion L. Keller, Subhasish Mukherjee, Mario Konijnenburg, Erik Jan Marinissen, Sandeep Kumar Goel
Automation of 3D-DfT Insertion. Asian Test Symposium (2011)
Anis Uzzaman, Brion L. Keller, Brian Foutz, Sandeep Bhatia, Thomas Bartenstein, Masayuki Arai, Kazuhiko Iwasaki
Reduction of Test Data Volume and Improvement of Diagnosability Using Hybrid Compression. IEICE Trans. Inf. Syst. (1) (2010)
Brion L. Keller, Krishna Chakravadhanula, Brian Foutz, Vivek Chickermane, R. Malneedi, Thomas J. Snethen, Vikram Iyengar, David E. Lackey, Gary Grise
Low cost at-speed testing using On-Product Clock Generation compatible with test compression. ITC (2010)
Brion L. Keller, Dale Meehl, Anis Uzzaman, Richard Billings
A Partially-Exhaustive Gate Transition Fault Model. Asian Test Symposium (2009)
Krishna Chakravadhanula, Vivek Chickermane, Brion L. Keller, Patrick R. Gallagher Jr., Prashant Narang
Capture power reduction using clock gating aware test generation. ITC (2009)
Rohit Kapur, Paul Reuter, Sandeep Bhatia, Brion L. Keller
CTL and Its Usage in the EDA Industry. IEEE Des. Test Comput. 26 (1) (2009)
Krishna Chakravadhanula, Vivek Chickermane, Brion L. Keller, Patrick R. Gallagher Jr., Anis Uzzaman
Why is Conventional ATPG Not Sufficient for Advanced Low Power Designs?. Asian Test Symposium (2009)
Anis Uzzaman, Brion L. Keller, Thomas J. Snethen, Kazuhiko Iwasaki, Masayuki Arai
Automatic Handling of Programmable On-Product Clock Generation (OPCG) Circuitry for Low Power Aware Delay Test. J. Low Power Electron. 5 (4) (2009)
Krishna Chakravadhanula, Vivek Chickermane, Brion L. Keller, Patrick R. Gallagher Jr., Steven Gregor
Test Generation for State Retention Logic. ATS (2008)
Brion L. Keller, Sandeep Bhatia, Thomas Bartenstein, Brian Foutz, Anis Uzzaman
Optimizing Test Data Volume Using Hybrid Compression. ATS (2008)
Brion L. Keller, Anis Uzzaman, Bibo Li, Thomas J. Snethen
Using Programmable On-Product Clock Generation (OPCG) for Delay Test. ATS (2007)
Brion L. Keller, Tom Jackson, Anis Uzzaman
A Review of Power Strategies for DFT and ATPG. ATS (2007)
Anis Uzzaman, Bibo Li, Thomas J. Snethen, Brion L. Keller, Gary Grise
Automated handling of programmable on-product clock generation (OPCG) circuitry for delay test vector generation. ITC (2007)
Bruce Cory, Rohit Kapur, Mick Tegethoff, Mark Kassab, Brion L. Keller, Kee Sup Kim, Dwayne Burek, Steven F. Oakland, Benoit Nadeau-Dostie
OCI: Open Compression Interface. ITC (2006)
Anis Uzzaman, Brion L. Keller, Vivek Chickermane
A Scalable Architecture for On-Chip Compression: Options and Trade-Offs. ATS (2006)
Brion L. Keller, Thomas Bartenstein
Use of MISRs for compression and diagnostics. ITC (2005)
Vivek Chickermane, Brion L. Keller, Kevin McCauley, Anis Uzzaman
Practical Aspects of Delay Testing for Nanometer Chips. Asian Test Symposium (2005)
Brion L. Keller
on-chip compression. ITC (2005)
Hiroyuki Nakamura, Akio Shirokane, Yoshihito Nishizaki, Anis Uzzaman, Vivek Chickermane, Brion L. Keller, Tsutomu Ube, Yoshihiko Terauchi
Low Cost Delay Testing of Nanometer SoCs Using On-Chip Clocking and Test Compression. Asian Test Symposium (2005)
Vivek Chickermane, Brian Foutz, Brion L. Keller
Channel Masking Synthesis for Efficient On-Chip Test Compression. ITC (2004)
Brion L. Keller, Mick Tegethoff, Thomas Bartenstein, Vivek Chickermane
An Economic Analysis and ROI Model for Nanometer Test. ITC (2004)
Carl Barnhart, Vanessa Brunkhorst, Frank Distler, Owen Farnsworth, Andrew Ferko, Brion L. Keller, David Scott, Bernd Könemann, Takeshi Onodera
Extending OPMISR beyond 10x Scan Test Efficiency. IEEE Des. Test Comput. 19 (5) (2002)
Amit K. Varshney, Bapiraju Vinnakota, Eric Skuldt, Brion L. Keller
High Performance Parallel Fault Simulation. ICCD (2001)
Rohit Kapur, Maurice Lousberg, Tony Taylor, Brion L. Keller, Paul Reuter, Douglas Kay
CTL the language for describing core-based test. ITC (2001)
Carl Barnhart, Vanessa Brunkhorst, Frank Distler, Owen Farnsworth, Brion L. Keller, Bernd Könemann, Andrej Ferko
OPMISR: the foundation for compressed ATPG vectors. ITC (2001)
Bernd Könemann, Carl Barnhart, Brion L. Keller, Thomas J. Snethen, Owen Farnsworth, Donald L. Wheater
A SmartBIST Variant with Guaranteed Encoding. Asian Test Symposium (2001)
Robert Butler, Brion L. Keller, Sarala Paliwal, Richard Schoonover, Joseph Swenton
Design and implementation of a parallel automatic test pattern generation algorithm with low test vector count. ITC (2000)
Paul Chang, Brion L. Keller, Sarala Paliwal
Effective parallel processing techniques for the generation of test data for a logic built-in self test system. Asian Test Symposium (2000)
Brion L. Keller
Using STIL to describe embedded core test requirements. ITC (1999)
Paul Chang, Brion L. Keller, Sarala Paliwal
Design and Implementation of a Parallel Weighted Random Pattern and Logic Built in Self Test Algorithm. ICCD (1999)
Brion L. Keller, Kevin McCauley, Joseph Swenton, James Youngs
ATPG in practical and non-traditional applications. ITC (1998)
Pamela S. Gillis, Tom S. Guzowski, Brion L. Keller, Randal H. Kerr
Test methodologies and design automation for IBM ASICs. IBM J. Res. Dev. 40 (4) (1996)
Bernd Könemann, J. Barlow, Paul Chang, R. Gabrielson, C. Goertz, Brion L. Keller, Kevin McCauley, J. Tischer, Vijay S. Iyengar, Barry K. Rosen, T. Williams
Delay Test: The Next Frontier for LSSD Test Systems. ITC (1992)
Brion L. Keller, David P. Carlson, William Maloney
The Compiled Logic Simulator. IEEE Des. Test Comput. 8 (1) (1991)
Brion L. Keller, David A. Haynes
Series Processors. ICCD (1991)