Erik Jan Marinissen

ORCID

Publication Activity (10 Years)

Years Active: 1998-2024
Publications (10 Years): 64

Top Venues

Publications

Erik Jan Marinissen, Harish Dattatraya Dixit, Ronald Shawn Blanton, Aaron Kuo, Wei Li, Subhasish Mitra, Chris Nigh, Ruben Purdy, Ben Kaczer, Dishant Sangani, Pieter Weckx, Philippe J. Roussel, Georges G. E. Gielen
Silent Data Corruption: Test or Reliability Problem? ETS (2024)
Sicong Yuan, Mohammad Amin Yaldagard, Hanzhi Xun, Moritz Fieback, Erik Jan Marinissen, Woojin Kim, Siddharth Rao, Sebastien Couet, Mottaqiallah Taouil, Said Hamdioui
Design-for-Test for Intermittent Faults in STT-MRAMs. ETS (2024)
Dishant Sangani, Ben Kaczer, Pieter Weckx, Philippe J. Roussel, Subrat Mishra, Erik Jan Marinissen, Georges G. E. Gielen
Possible Origins, Identification, and Screening of Silent Data Corruption in Data Centers. IRPS (2024)
Zhan Gao, Min-Chun Hu, Rogier Baert, Bilal Chehab, Joe Swenton, Santosh Malagi, Jos Huisken, Kees Goossens, Erik Jan Marinissen
Cell-Aware Test on Various Circuits in an Advanced 3-nm Technology. IEEE Des. Test 41 (2) (2024)
Erik Jan Marinissen, Adrian Evans, Po-Yao Chuang, Martin Keim, Anshuman Chandra
New Standard-under-Development for Chiplet Interconnect Test and Repair: IEEE Std P3405. ETS (2024)
Tsung-Hsuan Wang, Po-Yao Chuang, Francesco Lorenzelli, Erik Jan Marinissen
Test and Repair Improvements for UCIe. ETS (2024)
Erik Jan Marinissen, Vineet Pancholi, Po-Yao Chuang, Martin Keim
IEEE Std P3405: New Standard-under-Development for Chiplet Interconnect Test and Repair. VTS (2024)
Po-Yao Chuang, Francesco Lorenzelli, Sreejit Chakravarty, Cheng-Wen Wu, Georges G. E. Gielen, Erik Jan Marinissen
Effective and Efficient Testing of Large Numbers of Inter-Die Interconnects in Chiplet-Based Multi-Die Packages. VTS (2023)
Po-Yao Chuang, Francesco Lorenzelli, Sreejit Chakravarty, Slimane Boutobza, Cheng-Wen Wu, Georges G. E. Gielen, Erik Jan Marinissen
Effective and Efficient Test and Diagnosis Pattern Generation for Many Inter-Die Interconnects in Chiplet-Based Packages. 3DIC (2023)
Ahmed Aouichi, Sicong Yuan, Moritz Fieback, Siddharth Rao, Woojin Kim, Erik Jan Marinissen, Sebastien Couet, Mottaqiallah Taouil, Said Hamdioui
Device Aware Diagnosis for Unique Defects in STT-MRAMs. ATS (2023)
Sicong Yuan, Z. Zhang, Moritz Fieback, Hanzhi Xun, Erik Jan Marinissen, Gouri Sankar Kar, Sidharth Rao, Sebastien Couet, M. Taouil, Said Hamdioui
Magnetic Coupling Based Test Development for Contact and Interconnect Defects in STT-MRAMs. ITC (2023)
Bapi Vinnakota, Jaber Derakhshandeh, Eric Beyne, Erik Jan Marinissen, Sreejit Chakravarty
IP Session on Chiplet: Design, Assembly, and Test. VTS (2023)
Sicong Yuan, Mottaqiallah Taouil, Moritz Fieback, Hanzhi Xun, Erik Jan Marinissen, Gouri Sankar Kar, Sidharth Rao, Sebastien Couet, Said Hamdioui
Device-Aware Test for Back-Hopping Defects in STT-MRAMs. DATE (2023)
Erik Jan Marinissen
Moore Meets Murphy : Invited Talk 1. ITC-Asia (2023)
Po-Yao Chuang, Francesco Lorenzelli, Erik Jan Marinissen
Generating Test Patterns for Chiplet Interconnects: Achieving Optimal Effectiveness and Efficiency. ITC-Asia (2023)
Francesco Lorenzelli, Asser Elsayed, Clement Godfrin, Alexander Grill, Stefan Kubicek, Ruoyu Li, Michele Stucchi, Danny Wan, Kristiaan De Greve, Erik Jan Marinissen, Georges G. E. Gielen
Wafer-Scale Electrical Characterization of Silicon Quantum Dots from Room to Low Temperatures. ITC (2023)
Francesco Lorenzelli, Asser Elsayed, Clement Godfrin, Alexander Grill, Stefan Kubicek, Ruoyu Li, Michele Stucchi, Danny Wan, Kristiaan De Greve, Erik Jan Marinissen, Georges G. E. Gielen
Study of Transistor Metrics for Room-Temperature Screening of Single Electron Transistors for Silicon Spin Qubit Applications. ETS (2023)
Lizhou Wu, Siddharth Rao, Mottaqiallah Taouil, Erik Jan Marinissen, Gouri Sankar Kar, Said Hamdioui
Characterization, Modeling, and Test of Intermediate State Defects in STT-MRAMs. IEEE Trans. Computers 71 (9) (2022)
Adam Cron, Hailong Jiao, Erik Jan Marinissen
Guest Editors' Introduction: Special Issue on Design and Test of Multidie Packages. IEEE Des. Test 39 (5) (2022)
Xugang Cao, Hailong Jiao, Erik Jan Marinissen
A Bypassable Scan Flip-Flop for Low Power Testing With Data Retention Capability. IEEE Trans. Circuits Syst. II Express Briefs 69 (2) (2022)
Kazuki Monta, Leonidas Katselas, Ferenc Fodor, Takuji Miki, Alkis A. Hatzopoulos, Makoto Nagata, Erik Jan Marinissen
Testing Embedded Toggle Generation Through On-Chip IR-Drop Measurements. IEEE Des. Test 39 (5) (2022)
Lizhou Wu, Siddharth Rao, Mottaqiallah Taouil, Erik Jan Marinissen, Gouri Sankar Kar, Said Hamdioui
MFA-MTJ Model: Magnetic-Field-Aware Compact Model of pMTJ for Robust STT-MRAM Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (11) (2022)
Francesco Lorenzelli, Zhan Gao, Joe Swenton, Santosh Malagi, Erik Jan Marinissen
Speeding up Cell-Aware Library Characterization by Preceding Simulation with Structural Analysis. ETS (2021)
Lizhou Wu, Siddharth Rao, Mottaqiallah Taouil, Erik Jan Marinissen, Gouri Sankar Kar, Said Hamdioui
Testing STT-MRAM: Manufacturing Defects, Fault Models, and Test Solutions. ITC (2021)
Yu-Rong Jian, Ferenc Fodor, Cheng-Wen Wu, Erik Jan Marinissen
Automated Probe-Mark Analysis for Advanced Probe Technology Characterization. IEEE Des. Test 38 (5) (2021)
Adam Cron, Erik Jan Marinissen, Riccardo Mariani
IEEE Standard 1838 Is on the Move. Computer 54 (11) (2021)
Kazuki Monta, Leonidas Katselas, Ferenc Fodor, Alkis A. Hatzopoulos, Makoto Nagata, Erik Jan Marinissen
Testing Embedded Toggle Pattern Generation Through On-Chip IR Drop Monitoring. ETS (2021)
Lizhou Wu, Siddharth Rao, Mottaqiallah Taouil, Erik Jan Marinissen, Gouri Sankar Kar, Said Hamdioui
Characterization and Fault Modeling of Intermediate State Defects in STT-MRAM. DATE (2021)
Zhan Gao, Min-Chun Hu, Santosh Malagi, Joe Swenton, Jos Huisken, Kees Goossens, Erik Jan Marinissen
Reducing Library Characterization Time for Cell-aware Test while Maintaining Test Quality. J. Electron. Test. 37 (2) (2021)
Lizhou Wu, Siddharth Rao, Mottaqiallah Taouil, Guilherme Cardoso Medeiros, Moritz Fieback, Erik Jan Marinissen, Gouri Sankar Kar, Said Hamdioui
Defect and Fault Modeling Framework for STT-MRAM Testing. IEEE Trans. Emerg. Top. Comput. 9 (2) (2021)
Lizhou Wu, Siddharth Rao, Mottaqiallah Taouil, Erik Jan Marinissen, Gouri Sankar Kar, Said Hamdioui
Impact of Magnetic Coupling and Density on STT-MRAM Performance. CoRR (2020)
Lizhou Wu, Mottaqiallah Taouil, Siddharth Rao, Erik Jan Marinissen, Said Hamdioui
Survey on STT-MRAM Testing: Failure Mechanisms, Fault Models, and Tests. CoRR (2020)
Michele Stucchi, Ferenc Fodor, Erik Jan Marinissen
Accurate Measurements of Small Resistances in Vertical Interconnects with Small Aspect Ratios. ETS (2020)
Lizhou Wu, Siddharth Rao, Mottaqiallah Taouil, Erik Jan Marinissen, Gouri Sankar Kar, Said Hamdioui
Impact of Magnetic Coupling and Density on STT-MRAM Performance. DATE (2020)
Min-Chun Hu, Zhan Gao, Santosh Malagi, Joe Swenton, Jos Huisken, Kees Goossens, Cheng-Wen Wu, Erik Jan Marinissen
Tightening the Mesh Size of the Cell-Aware ATPG Net for Catching All Detectable Weakest Faults. ETS (2020)
Lizhou Wu, Siddharth Rao, Mottaqiallah Taouil, Erik Jan Marinissen, Gouri Sankar Kar, Said Hamdioui
Characterization, Modeling and Test of Synthetic Anti-Ferromagnet Flip Defect in STT-MRAMs. ITC (2020)
Dimitrios Velenis, Joeri De Vos, Soon-Wook Kim, Jaber Derakhshandeh, Pieter Bex, Giovanni Capuz, Samuel Suhard, Kenneth June Rebibis, Stefaan Van Huylenbroeck, Erik Jan Marinissen, Alain Phommahaxay, Andy Miller, Gerald Beyer, Geert Van der Plas, Eric Beyne
Process Complexity and Cost Considerations of Multi-Layer Die Stacks. 3DIC (2019)
Zhan Gao, Santosh Malagi, Min-Chun Hu, Joe Swenton, Rogier Baert, Jos Huisken, Bilal Chehab, Kees Goossens, Erik Jan Marinissen
Application of Cell-Aware Test on an Advanced 3nm CMOS Technology Library. ITC (2019)
Moritz Fieback, Lizhou Wu, Guilherme Cardoso Medeiros, Hassen Aziza, Siddharth Rao, Erik Jan Marinissen, Mottaqiallah Taouil, Said Hamdioui
Device-Aware Test: A New Test Approach Towards DPPB Level. ITC (2019)
Zhan Gao, Santosh Malagi, Erik Jan Marinissen, Joe Swenton, Jos Huisken, Kees Goossens
Defect-Location Identification for Cell-Aware Test. LATS (2019)
Zhan Gao, Min-Chun Hu, Joe Swenton, Santosh Malagi, Jos Huisken, Kees Goossens, Erik Jan Marinissen
Optimization of Cell-Aware ATPG Results by Manipulating Library Cells' Defect Detection Matrices. ITC-Asia (2019)
Lizhou Wu, Siddharth Rao, Guilherme Cardoso Medeiros, Mottaqiallah Taouil, Erik Jan Marinissen, Farrukh Yasin, Sebastien Couet, Said Hamdioui, Gouri Sankar Kar
Pinhole Defect Characterization and Fault Modeling for STT-MRAM Testing. ETS (2019)
Harm van Schaaijk, Martien Spierings, Erik Jan Marinissen
Automatic Generation of In-Circuit Tests for Board Assembly Defects. ITC-Asia (2018)
Harm van Schaaijk, Martien Spierings, Erik Jan Marinissen
Automatic generation of in-circuit tests for board assembly defects. ETS (2018)
Erik Jan Marinissen, Ferenc Fodor, Arnita Podpod, Michele Stucchi, Yu-Rong Jian, Cheng-Wen Wu
Solutions to Multiple Probing Challenges for Test Access to Multi-Die Stacked Integrated Circuits. ITC (2018)
Lizhou Wu, Mottaqiallah Taouil, Siddharth Rao, Erik Jan Marinissen, Said Hamdioui
Electrical Modeling of STT-MRAM Defects. ITC (2018)
Leonidas Katselas, Alkis A. Hatzopoulos, Hailong Jiao, Christos Papameletis, Erik Jan Marinissen
On-Chip Toggle Generators to Provide Realistic Conditions during Test of Digital 2D-SoCs and 3D-SICs. ITC (2018)
Yu Li, Ming Shao, Hailong Jiao, Adam Cron, Sandeep Bhatia, Erik Jan Marinissen
IEEE Std P1838's flexible parallel port and its specification with Google's protocol buffers. ETS (2018)
Erik Jan Marinissen, Yervant Zorian
Guest Editors' Introduction: Design & Test of a High-Volume 3-D Stacked Graphics Processor With High-Bandwidth Memory. IEEE Des. Test 34 (1) (2017)
Leonidas Katselas, Hailong Jiao, Angelos Athanasiadis, Christos Papameletis, Alkis A. Hatzopoulos, Erik Jan Marinissen
Embedded toggle generator to control the switching activity during test of digital 2D-SoCs and 3D-SICs. PATMOS (2017)
Erik Jan Marinissen, Ferenc Fodor, Bart De Wachter, Jorg Kiesewetter, Eric Hill, Ken Smith
A fully automatic test system for characterizing large-array fine-pitch micro-bump probe cards. ITC-Asia (2017)
Erik Jan Marinissen, Teresa L. McLaurin, Hailong Jiao
IEEE Std P1838: DfT standard-under-development for 2.5D-, 3D-, and 5.5D-SICs. ETS (2016)
Jeroen De Coster, Peter De Heyn, Marianna Pantouvaki, Brad Snyder, Hongtao Chen, Erik Jan Marinissen, Philippe Absil, Joris Van Campenhout, Bryan Bolt
Test-station for flexible semi-automatic wafer-level silicon photonics testing. ETS (2016)
S. Saqib Khursheed, Pascal Vivet, Fabian Hopsch, Erik Jan Marinissen
Guest Editors' Introduction: Robust 3-D Stacked ICs. IEEE Des. Test 33 (3) (2016)
Erik Jan Marinissen, Yervant Zorian, Mario Konijnenburg, Chih-Tsun Huang, Ping-Hsuan Hsieh, Peter Cockburn, Jeroen Delvaux, Vladimir Rozic, Bohan Yang, Dave Singelée, Ingrid Verbauwhede, Cedric Mayor, Robert Van Rijsinge, Cocoy Reyes
IoT: Source of test challenges. ETS (2016)
Sergej Deutsch, Krishnendu Chakrabarty, Erik Jan Marinissen
Robust Optimization of Test-Access Architectures Under Realistic Scenarios. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34 (11) (2015)
Mottaqiallah Taouil, Said Hamdioui, Erik Jan Marinissen
Yield Improvement for 3D Wafer-to-Wafer Stacked ICs Using Wafer Matching. ACM Trans. Design Autom. Electr. Syst. 20 (2) (2015)
Konstantin Shibin, Vivek Chickermane, Brion L. Keller, Christos Papameletis, Erik Jan Marinissen
At-Speed Testing of Inter-Die Connections of 3D-SICs in the Presence of Shore Logic. ATS (2015)
Dimitrios Velenis, Mikael Detalle, Geert Hellings, Mirko Scholz, Erik Jan Marinissen, Geert Van der Plas, Antonio La Manna, Andy Miller, Dimitri Linten, Eric Beyne
Processing active devices on Si interposer and impact on cost. 3DIC (2015)
Mottaqiallah Taouil, Mahmoud Masadeh, Said Hamdioui, Erik Jan Marinissen
Post-Bond Interconnect Test and Diagnosis for 3-D Memory Stacked on Logic. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34 (11) (2015)
Geert Hellings, Mirko Scholz, Mikael Detalle, Dimitrios Velenis, Muriel de Potter de ten Broeck, C. Roda Neve, Y. Li, Stefaan Van Huylenbroeck, Shih-Hung Chen, Erik Jan Marinissen, Antonio La Manna, Geert Van der Plas, Dimitri Linten, Eric Beyne, Aaron Thean
Active-lite interposer for 2.5 & 3D integration. VLSIC (2015)
Erik Jan Marinissen, Bart De Wachter, Teng Wang, Jens Fiedler, Jorg Kiesewetter, Karsten Stoll
Automated testing of bare die-to-die stacks. ITC (2015)
Urban Ingelsson, Sandeep Kumar Goel, Erik Larsson, Erik Jan Marinissen
Abort-on-Fail Test Scheduling for Modular SOCs without and with Preemption. IEEE Trans. Computers 64 (12) (2015)
Christos Papameletis, Brion L. Keller, Vivek Chickermane, Said Hamdioui, Erik Jan Marinissen
A DfT Architecture and Tool Flow for 3-D SICs With Test Data Compression, Embedded Cores, and Multiple Towers. IEEE Des. Test 32 (4) (2015)
Erik Jan Marinissen, Bart De Wachter, Ken Smith, Jorg Kiesewetter, Mottaqiallah Taouil, Said Hamdioui
Direct probing on large-array fine-pitch micro-bumps of a wide-I/O logic-memory interface. ITC (2014)
Mottaqiallah Taouil, Mahmoud Masadeh, Said Hamdioui, Erik Jan Marinissen
Interconnect test for 3D stacked memory-on-logic. DATE (2014)
Chun-Chuan Chi, Erik Jan Marinissen, Sandeep Kumar Goel, Cheng-Wen Wu
Low-Cost Post-Bond Testing of 3-D ICs Containing a Passive Silicon Interposer Base. IEEE Trans. Very Large Scale Integr. Syst. 22 (11) (2014)
Mottaqiallah Taouil, Said Hamdioui, Erik Jan Marinissen
Quality versus cost analysis for 3D Stacked ICs. VTS (2014)
Erik Jan Marinissen, Bart De Wachter, Stephen O'Loughlin, Sergej Deutsch, Christos Papameletis, Tobias Burgherr
Vesuvius-3D: A 3D-DfT demonstrator. ITC (2014)
Erik Jan Marinissen
Murphy goes 3D. ISVLSI (2013)
Mottaqiallah Taouil, Said Hamdioui, Erik Jan Marinissen, Sudipta Bhawmik
Impact of mid-bond testing in 3D stacked ICs. DFTS (2013)
Erik Jan Marinissen
Creating options for 3D-SIC testing. VLSI-DAT (2013)
Christos Papameletis, Brion L. Keller, Vivek Chickermane, Erik Jan Marinissen, Said Hamdioui
Automated DfT insertion and test generation for 3D-SICs with embedded cores and multiple towers. ETS (2013)
Dragomir Milojevic, Pol Marchal, Erik Jan Marinissen, Geert Van der Plas, Diederik Verkest, Eric Beyne
Design issues in heterogeneous 3D/2.5D integration. ASP-DAC (2013)
Erik Jan Marinissen
Creating options for 3D-SIC testing. DDECS (2013)
Sergej Deutsch, Krishnendu Chakrabarty, Erik Jan Marinissen
Uncertainty-aware robust optimization of test-access architectures for 3D stacked ICs. ITC (2013)
Dimitrios Velenis, Mikael Detalle, Erik Jan Marinissen, Eric Beyne
Si interposer build-up options and impact on 3D system cost. 3DIC (2013)
Mottaqiallah Taouil, Said Hamdioui, Erik Jan Marinissen, Sudipta Bhawmik
Using 3D-COSTAR for 2.5D test cost optimization. 3DIC (2013)
Mottaqiallah Taouil, Said Hamdioui, Kees Beenakker, Erik Jan Marinissen
Test Impact on the Overall Die-to-Wafer 3D Stacked IC Cost. J. Electron. Test. 28 (1) (2012)
Erik Jan Marinissen, Chun-Chuan Chi, Mario Konijnenburg, Jouke Verbree
A DfT Architecture for 3D-SICs Based on a Standardizable Die Wrapper. J. Electron. Test. 28 (1) (2012)
Erik Jan Marinissen, Yervant Zorian
Guest Editorial: Special Issue on Testing of 3D Stacked Integrated Circuits. J. Electron. Test. 28 (1) (2012)
Erik Jan Marinissen
Challenges and emerging solutions in testing TSV-based 2 1 over 2D- and 3D-stacked ICs. DATE (2012)
Brandon Noia, Krishnendu Chakrabarty, Erik Jan Marinissen
Optimization Methods for Post-Bond Testing of 3D Stacked ICs. J. Electron. Test. 28 (1) (2012)
Sergej Deutsch, Brion L. Keller, Vivek Chickermane, Subhasish Mukherjee, Navdeep Sood, Sandeep Kumar Goel, Ji-Jan Chen, Ashok Mehta, Frank Lee, Erik Jan Marinissen
DfT architecture and ATPG for Interconnect tests of JEDEC Wide-I/O memory-on-logic die stacks. ITC (2012)
Erik Jan Marinissen
Pioneering in Asia With the US Venture Capital Model. IEEE Des. Test Comput. 29 (6) (2012)
Erik Jan Marinissen, Gilbert Vandling, Sandeep Kumar Goel, Friedrich Hapke, Jason Rivers, Nikolaus Mittermaier, Swapnil Bahl
EDA solutions to new-defect detection in advanced process technologies. DATE (2012)
Ken Smith, Peter Hanaway, Mike Jolley, Reed Gleason, Eric Strid, Tom Daenen, Luc Dupas, Bruno Knuts, Erik Jan Marinissen, Marc Van Dievel
Evaluation of TSV and micro-bump probing for wide I/O testing. ITC (2011)
Sergej Deutsch, Vivek Chickermane, Brion L. Keller, Subhasish Mukherjee, Mario Konijnenburg, Erik Jan Marinissen, Sandeep Kumar Goel
Automation of 3D-DfT Insertion. Asian Test Symposium (2011)
Chun-Chuan Chi, Erik Jan Marinissen, Sandeep Kumar Goel, Cheng-Wen Wu
Post-bond testing of 2.5D-SICs and 3D-SICs containing a passive silicon interposer base. ITC (2011)
Chun-Chuan Chi, Erik Jan Marinissen, Sandeep Kumar Goel, Cheng-Wen Wu
Multi-visit TAMs to Reduce the Post-Bond Test Length of 2.5D-SICs with a Passive Silicon Interposer Base. Asian Test Symposium (2011)
Brandon Noia, Krishnendu Chakrabarty, Sandeep Kumar Goel, Erik Jan Marinissen, Jouke Verbree
Test-Architecture Optimization and Test Scheduling for TSV-Based 3-D Stacked ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30 (11) (2011)
Chun-Chuan Chi, Erik Jan Marinissen, Sandeep Kumar Goel, Cheng-Wen Wu
DfT Architecture for 3D-SICs with Multiple Towers. ETS (2011)
Mottaqiallah Taouil, Said Hamdioui, Erik Jan Marinissen
On modeling and optimizing cost in 3D Stacked-ICs. IDT (2011)
Erik Jan Marinissen, Adit D. Singh, Dan Glotter, Marco Esposito, John M. Carulli Jr., Amit Nahar, Kenneth M. Butler, Davide Appello, Chris Portelli
Adapting to adaptive testing. DATE (2010)
Jouke Verbree, Erik Jan Marinissen, Philippe Roussel, Dimitrios Velenis
On the cost-effectiveness of matching repositories of pre-tested wafers for wafer-to-wafer 3D chip stacking. ETS (2010)
Dimitrios Velenis, Erik Jan Marinissen, Eric Beyne
Cost effectiveness of 3D integration options. 3DIC (2010)
Erik Jan Marinissen, Jouke Verbree, Mario Konijnenburg
A structured and scalable test access architecture for TSV-based 3D stacked ICs. VTS (2010)
Brandon Noia, Sandeep Kumar Goel, Krishnendu Chakrabarty, Erik Jan Marinissen, Jouke Verbree
Test-architecture optimization for TSV-based 3D stacked ICs. ETS (2010)
Mottaqiallah Taouil, Said Hamdioui, Kees Beenakker, Erik Jan Marinissen
Test Cost Analysis for 3D Die-to-Wafer Stacking. Asian Test Symposium (2010)
Erik Jan Marinissen
Testing TSV-based three-dimensional stacked ICs. DATE (2010)

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Publication Activity (10 Years)

Top Topics

Top Venues

Erik Jan Marinissen