Sudipta Bhawmik

Publication Activity (10 Years)

Years Active: 1988-2015
Publications (10 Years): 2

Top Topics

Test Generation

Optimization Process

Top Venues

ACM Trans. Design Autom. Electr. Syst.

Publications

Ran Wang, Krishnendu Chakrabarty, Sudipta Bhawmik
Built-In Self-Test and Test Scheduling for Interposer-Based 2.5D IC. ACM Trans. Design Autom. Electr. Syst. 20 (4) (2015)
Ran Wang, Krishnendu Chakrabarty, Sudipta Bhawmik
Interconnect Testing and Test-Path Scheduling for Interposer-Based 2.5-D ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34 (1) (2015)
Ran Wang, Krishnendu Chakrabarty, Sudipta Bhawmik
At-speed interconnect testing and test-path optimization for 2.5D ICs. VTS (2014)
Ran Wang, Krishnendu Chakrabarty, Sudipta Bhawmik
Built-in self-test for interposer-based 2.5D ICs. ICCD (2014)
Mottaqiallah Taouil, Said Hamdioui, Erik Jan Marinissen, Sudipta Bhawmik
Impact of mid-bond testing in 3D stacked ICs. DFTS (2013)
Mottaqiallah Taouil, Said Hamdioui, Erik Jan Marinissen, Sudipta Bhawmik
Using 3D-COSTAR for 2.5D test cost optimization. 3DIC (2013)
Michael G. Wahl, Sudipta Bhawmik, Kamran Zarrineh, Pradipta Ghosh, Scott Davidson, Peter Harrod
The P1500 DFT Disclosure Document: A Standard to Communicate Mergeable Core DFT Data. ITC (2003)
Subhayu Basu, Indranil Sengupta, Dipanwita Roy Chowdhury, Sudipta Bhawmik
An Integrated Approach to Testing Embedded Cores and Interconnects Using Test Access Mechanism (TAM) Switch. J. Electron. Test. 18 (4-5) (2002)
Subhayu Basu, Debdeep Mukhopadhyay, Dipanwita Roy Chowdhury, Indranil Sengupta, Sudipta Bhawmik
Reformatting Test Patterns for Testing Embedded Core Based System Using Test Access Mechanism (TAM) Switch. VLSI Design (2002)
Sudipta Bhawmik
Introduction to SystemC. VLSI Design (2001)
Indradeep Ghosh, Niraj K. Jha, Sudipta Bhawmik
A BIST scheme for RTL circuits based on symbolic testabilityanalysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19 (1) (2000)
Huan-Chih Tsai, Kwang-Ting Cheng, Sudipta Bhawmik
On improving test quality of scan-based BIST. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19 (8) (2000)
Frank P. Higgins, Sudipta Bhawmik
Core Based ASIC Design. VLSI Design (2000)
Huan-Chih Tsai, Kwang-Ting Cheng, Sudipta Bhawmik
Improving the Test Quality for Scan-Based BIST Using a General Test Application Scheme. DAC (1999)
Xiaodong Zhang, Kaushik Roy, Sudipta Bhawmik
POWERTEST: A Tool for Energy Conscious Weighted Random Pattern Testing. VLSI Design (1999)
Huan-Chih Tsai, Kwang-Ting Cheng, Chih-Jen Lin, Sudipta Bhawmik
Efficient test-point selection for scan-based BIST. IEEE Trans. Very Large Scale Integr. Syst. 6 (4) (1998)
Indradeep Ghosh, Niraj K. Jha, Sudipta Bhawmik
A BIST Scheme for RTL Controller-Data Paths Based on Symbolic Testability Analysis. DAC (1998)
Huan-Chih Tsai, Sudipta Bhawmik, Kwang-Ting Cheng
An almost full-scan BIST solution-higher fault coverage and shorter test application time. ITC (1998)
Nilanjan Mukherjee, Tapan J. Chakraborty, Sudipta Bhawmik
A BIST scheme for the detection of path-delay faults. ITC (1998)
Sudipta Bhawmik, Indradeep Ghosh
A Practical Method for Selecting Partial Scan Flip-flops for Large Circuits. VLSI Design (1997)
Huan-Chih Tsai, Kwang-Ting Cheng, Chih-Jen Lin, Sudipta Bhawmik
A Hybrid Algorithm for Test Point Selection for Scan-Based BIST. DAC (1997)
Chih-Jen Lin, Yervant Zorian, Sudipta Bhawmik
Integration of partial scan and built-in self-test. J. Electron. Test. 7 (1-2) (1995)
Chih-Jen Lin, Yervant Zorian, Sudipta Bhawmik
PSBIST: A Partial-Scan Based Built-In Self-Test Scheme. ITC (1993)
Tapan J. Chakraborty, Sudipta Bhawmik, Robert Bencivenga, Chih-Jen Lin
Test Sets Using Partial Scan. DAC (1991)
Anurag Acharya, Sudipta Bhawmik, C. R. K. Prasad, P. Palchaudhuri
KIDLAN: A hardware description language. Microprocessing and Microprogramming 26 (1) (1989)
Sudipta Bhawmik, Parimal Pal Chaudhuri
Expert system to configure global design for testability structure in a VLSI circuit. Microprocess. Microsystems 13 (7) (1989)
Prasad R. Chalasani, Sudipta Bhawmik, Anurag Acharya, Parimal Pal Chaudhuri
Design of Testable VLSI Circuits with Minumum Area Overhead. IEEE Trans. Computers 38 (10) (1989)
Sudipta Bhawmik, V. K. Narang, Parimal Pal Chaudhuri
Selecting test methodologies for PLAs and random logic modules in VLSI circuits - an expert systems approach. Integr. 7 (3) (1989)
Sudipta Bhawmik, P. Palchaudhuri
DFT Expert: designing testable VLSI circuits. IEEE Des. Test 6 (5) (1989)
Sudipta Bhawmik, Parimal Pal Chaudhuri
DFTEXPERT: An Expert System for Design of Testable VLSI Circuits. IEA/AIE (Vol. 1) (1988)