Tapan J. Chakraborty

Publication Activity (10 Years)

Years Active: 1988-2013
Publications (10 Years): 0

Top Topics

Discrete Fourier Transform

Statistical Tests

Top Venues

Publications

Ujjwal Guin, Tapan J. Chakraborty, Mohammad Tehranipoor
Functional Fmax test-time reduction using novel DFTs for circuit initialization. ICCD (2013)
Michele Portolan, Suresh Goyal, Bradford G. Van Treuren, Chen-Huan Chiang, Tapan J. Chakraborty, Thomas B. Cook
A Common Language Framework for Next-Generation Embedded Testing. IEEE Des. Test Comput. 27 (5) (2010)
Michele Portolan, Suresh Goyal, Bradford G. Van Treuren, Chen-Huan Chiang, Tapan J. Chakraborty, Thomas B. Cook
A New Language Approach for IJTAG. ITC (2008)
Aditya Jagirdar, Roystein Oliveira, Tapan J. Chakraborty
A Robust Architecture for Flip-Flops Tolerant to Soft-Errors and Transients from Combinational Circuits. VLSI Design (2008)
Brendan Mullane, Chen-Huan Chiang, Michael Higgins, Ciaran MacNamee, Tapan J. Chakraborty, Thomas B. Cook
FPGA Prototyping of a Scan Based System-On-Chip Design. ReCoSoC (2007)
Tapan J. Chakraborty, Chen-Huan Chiang, Bradford G. Van Treuren
A practical approach to comprehensive system test & debug using boundary scan based test architecture. ITC (2007)
Roystein Oliveira, Aditya Jagirdar, Tapan J. Chakraborty
A TMR Scheme for SEU Mitigation in Scan Flip-Flops. ISQED (2007)
Tapan J. Chakraborty
Efficient Test Architecture based on Boundary Scan for Comprehensive System Test. Asian Test Symposium (2005)
Tapan J. Chakraborty, Chen-Huan Chiang
A Novel Fault Injection Method for System Verification Based on FPGA Boundary Scan Architectur. ITC (2002)
Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell
Path delay fault simulation of sequential circuits. IEEE Trans. Very Large Scale Integr. Syst. 8 (2) (2000)
Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell
Improving path delay testability of sequential circuits. IEEE Trans. Very Large Scale Integr. Syst. 8 (6) (2000)
Nilanjan Mukherjee, Tapan J. Chakraborty, Ramesh Karri
Built in self test: a complete test solution for telecommunication systems. IEEE Commun. Mag. 37 (6) (1999)
Nilanjan Mukherjee, Tapan J. Chakraborty, Sudipta Bhawmik
A BIST scheme for the detection of path-delay faults. ITC (1998)
Tapan J. Chakraborty, Vishwani D. Agrawal
Effective Path Selection for Delay Fault Testing of Sequential Circuits. ITC (1997)
Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell
On variable clock methods for path delay testing of sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16 (11) (1997)
Tapan J. Chakraborty, Vishwani D. Agrawal
Design for high-speed testability of stuck-at faults. VLSI Design (1996)
Vishwani D. Agrawal, Tapan J. Chakraborty
High-Performance Circuit Testing with Slow-Speed Testers. ITC (1995)
Tapan J. Chakraborty, Vishwani D. Agrawal
Robust testing for stuck-at faults. VLSI Design (1995)
Tapan J. Chakraborty, Vishwani D. Agrawal
Simulation of at-speed tests for stuck-at faults. VTS (1995)
Tapan J. Chakraborty, Vishwani D. Agrawal
Delay independent initialization of sequential circuits. Great Lakes Symposium on VLSI (1994)
Vishwani D. Agrawal, Tapan J. Chakraborty
Partial scan testing with single clock control. VTS (1993)
Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell
Design for Testability for Path Delay faults in Sequential Circuits. DAC (1993)
Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell
Delay Fault Models and Test Generation for Random Logic Sequential Circuits. DAC (1992)
Sumit Ghosh, Tapan J. Chakraborty
On behavior fault modeling for digital designs. J. Electron. Test. 2 (2) (1991)
Tapan J. Chakraborty, Sudipta Bhawmik, Robert Bencivenga, Chih-Jen Lin
Test Sets Using Partial Scan. DAC (1991)
Wu-Tung Cheng, Tapan J. Chakraborty
Gentest: An Automatic Test-Generation System for Sequential Circuits. Computer 22 (4) (1989)
Tapan J. Chakraborty, Sumit Ghosh
On Behavior Fault Modeling for Combinational Digital Designs. ITC (1988)