Design for Testability for Path Delay faults in Sequential Circuits.
Tapan J. ChakrabortyVishwani D. AgrawalMichael L. BushnellPublished in: DAC (1993)
Keyphrases
- case study
- analog circuits
- power dissipation
- circuit design
- logic synthesis
- knowledge based systems
- shortest path
- fault diagnosis
- software architecture
- design space
- design tools
- built in self test
- neural network
- chip design
- digital circuits
- low power
- design principles
- design process
- building blocks
- sufficient conditions
- mobile robot
- evolutionary algorithm
- genetic algorithm