Michael L. Bushnell

Publication Activity (10 Years)

Years Active: 1984-2009
Publications (10 Years): 0

Publications

Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell
Variable Input Delay CMOS Logic for Low Power Design. IEEE Trans. Very Large Scale Integr. Syst. 17 (10) (2009)
Hari Vijay Venkatanarayanan, Michael L. Bushnell
A Jitter Reduction Circuit Using Autocorrelation for Phase-Locked Loops and Serializer-Deserializer (SERDES) Circuits. VLSI Design (2008)
Rajamani Sethuram, Michael L. Bushnell, Vishwani D. Agrawal
Fault Nodes in Implication Graph for Equivalence/Dominance Collapsing, and Identifying Untestable and Independent Faults. VTS (2008)
Rohit Pandey, Michael L. Bushnell
Architecture for Variable-Length Combined FFT, DCT, and MWT Transform Hardware for a Multi-ModeWireless System. VLSI Design (2007)
Rajamani Sethuram, Omar I. Khan, Hari Vijay Venkatanarayanan, Michael L. Bushnell
A Neural Net Branch Predictor to Reduce Power. VLSI Design (2007)
Rajamani Sethuram, Seongmoon Wang, Srimat T. Chakradhar, Michael L. Bushnell
Zero Cost Test Point Insertion Technique for Structured ASICs. VLSI Design (2007)
Baozhen Yu, Michael L. Bushnell
Power Grid Analysis of Dynamic Power Cutoff Technology. ISCAS (2007)
Suresh Kumar Devanathan, Michael L. Bushnell
Test Pattern Generation Using Modulation by Haar Wavelets and Correlation for Sequential BIST. VLSI Design (2007)
Jeffrey Ayres, Michael L. Bushnell
Analog Circuit Testing Using Auto Regressive Moving Average Models. VLSI Design (2007)
Lan Rao, Michael L. Bushnell, Vishwani D. Agrawal
Signatures Reduce Defect Level and Yield Loss. IEEE Trans. Very Large Scale Integr. Syst. 15 (11) (2007)
Omar I. Khan, Michael L. Bushnell, Suresh Kumar Devanathan, Vishwani D. Agrawal
SPARTAN: a spectral and information theoretic approach to partial-scan. ITC (2007)
Daniel Mazor, Michael L. Bushnell, David J. Mulligan, Richard J. Blaikie
Fault Models and Device Yield of a Large Population of Room Temperature Operation Single-Electron Transistors. VLSI Design (2007)
Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell
Transistor Sizing of Logic Gates to Maximize Input Delay Variability. J. Low Power Electron. 2 (1) (2006)
Suresh Kumar Devanathan, Michael L. Bushnell
Sequential Spectral ATPG Using the Wavelet Transform and Compaction. VLSI Design (2006)
Hari Vijay Venkatanarayanan, Michael L. Bushnell
An Area Efficient Mixed-Signal Test Architecture for Systems-on-a-Chip. VLSI Design (2006)
Shweta Chary, Michael L. Bushnell
Analog Macromodeling for Combined Resistive Vias, Resistive Bridges, and Capacitive Crosstalk Delay Faults. VLSI Design (2006)
Omar I. Khan, Michael L. Bushnell
Aliasing Analysis of Spectral Statistical Response Compaction Techniques. VLSI Design (2006)
Baozhen Yu, Michael L. Bushnell
A novel dynamic power cutoff technique (DPCT) for active leakage reduction in deep submicron CMOS circuits. ISLPED (2006)
Shweta Chary, Michael L. Bushnell
Automatic Path-Delay Fault Test Generation for Combined Resistive Vias, Resistive Bridges, and Capacitive Crosstalk Delay Faults. VLSI Design (2006)
Rajamani Sethuram, Seongmoon Wang, Srimat T. Chakradhar, Michael L. Bushnell
Zero Cost Test Point Insertion Technique to Reduce Test Set Size and Test Generation Time for Structured ASICs. ATS (2006)
Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell
Design of Variable Input Delay Gates for Low Dynamic Power Circuits. PATMOS (2005)
Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell
Variable Input Delay CMOS Logic for Low Power Design. VLSI Design (2005)
Kunal K. Dave, Vishwani D. Agrawal, Michael L. Bushnell
Using Contrapositive Law in an Implication Graph to Identify Logic Redundancies. VLSI Design (2005)
Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell
A Tuturial on the Emerging Nanotechnology Devices. VLSI Design (2004)
Junwu Zhang, Michael L. Bushnell, Vishwani D. Agrawal
On Random Pattern Generation with the Selfish Gene Algorithm for Testing Digital Sequential Circuits. ITC (2004)
Subhashis Majumder, Bhargab B. Bhattacharya, Vishwani D. Agrawal, Michael L. Bushnell
A New Classification of Path-Delay Fault Testability in Terms of Stuck-at Faults. J. Comput. Sci. Technol. 19 (6) (2004)
Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell
CMOS Circuit Design for Minimum Dynamic Power and Highest Speed. VLSI Design (2004)
Omar I. Khan, Michael L. Bushnell
Spectral Analysis for Statistical Response Compaction During Built-In Self-Testing. ITC (2004)
Vishal J. Mehta, Kunal K. Dave, Vishwani D. Agrawal, Michael L. Bushnell
A Fault-Independent Transitive Closure Algorithm for Redundancy Identification. VLSI Design (2003)
Lan Rao, Michael L. Bushnell, Vishwani D. Agrawal
New Graphical IDDQ Signatures Reduce Defect Level and Yield Loss. VLSI Design (2003)
Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell
Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program. VLSI Design (2003)
Vishwani D. Agrawal, Michael L. Bushnell
Electronic Testing for SOC Designers (Tutorial Abstract). VLSI Design (2002)
Vivek Gaur, Vishwani D. Agrawal, Michael L. Bushnell
A New Transitive Closure Algorithm with Application to Redundancy Identification. DELTA (2002)
Aditya D. Sathe, Michael L. Bushnell, Vishwani D. Agrawal
Analog Macromodeling of Capacitive Coupling Faults in Digital Circuit Interconnects. ITC (2002)
Sanjay Mohan, Michael L. Bushnell
A Code Transition Delay Model for ADC Test. VLSI Design (2001)
Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell
Path delay fault simulation of sequential circuits. IEEE Trans. Very Large Scale Integr. Syst. 8 (2) (2000)
Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell
Improving path delay testability of sequential circuits. IEEE Trans. Very Large Scale Integr. Syst. 8 (6) (2000)
Marwan A. Gharaybeh, Vishwani D. Agrawal, Michael L. Bushnell, Carlos G. Parodi
False-Path Removal Using Delay Fault Simulation. J. Electron. Test. 16 (5) (2000)
Rajesh Ramadoss, Michael L. Bushnell
Test Generation for Mixed-Signal Devices Using Signal Flow Graphs. J. Electron. Test. 14 (3) (1999)
Madhu K. Iyer, Michael L. Bushnell
Effect of Noise on Analog Circuit Testing. J. Electron. Test. 15 (1-2) (1999)
Subhashis Majumder, Bhargab B. Bhattacharya, Vishwani D. Agrawal, Michael L. Bushnell
A Complete Characterization of Path Delay Faults through Stuck-at Faults. VLSI Design (1999)
Vishwani D. Agrawal, Michael L. Bushnell, Ganapathy Parthasarathy, Rajesh Ramadoss
Digital Circuit Design for Minimum Transient Energy and a Linear Programming Method. VLSI Design (1999)
Michael L. Bushnell
Increasing Test Coverage in a VLSI Design Course. ITC (1999)
Marwan A. Gharaybeh, Vishwani D. Agrawal, Michael L. Bushnell
False-Path Removal Using Delay Fault Simulation. Asian Test Symposium (1998)
Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal
The path-status graph with application to delay fault simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17 (4) (1998)
Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal
A parallel-vector concurrent-fault simulator and generation of single-input-change tests for path-delay faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17 (9) (1998)
Carlos G. Parodi, Vishwani D. Agrawal, Michael L. Bushnell, Shianling Wu
A non-enumerative path delay fault simulator for sequential circuits. ITC (1998)
Ganapathy Parthasarathy, Michael L. Bushnell
Towards Simultaneous Delay-Fault Built-In Self-Test and Partial-Scan Insertion. VTS (1998)
Subhashis Majumder, Michael L. Bushnell, Vishwani D. Agrawal
Path Delay Testing: Variable-Clock Versus Rated-Clock. VLSI Design (1998)
Lakshminarayana Pappu, Michael L. Bushnell, Vishwani D. Agrawal, Mandyam-Komar Srinivas
Statistical Delay Fault Coverage Estimation for Synchronous Sequential Circuits. J. Electron. Test. 12 (3) (1998)
Subhashis Majumder, Vishwani D. Agrawal, Michael L. Bushnell
On Delay-Untestable Paths and Stuck-Fault Redundancy. VTS (1998)
Madhu K. Iyer, Michael L. Bushnell
Effect of Noise on Analog Circuit Testing. VTS (1998)
Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell
On variable clock methods for path delay testing of sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16 (11) (1997)
Mandyam-Komar Srinivas, Michael L. Bushnell, Vishwani D. Agrawal
Flags and Algebra for Sequential Circuit VNR Path Delay Fault Test Generation. VLSI Design (1997)
Michael L. Bushnell, John Giraldi
A Functional Decomposition Method for Redundancy Identification and Test Generation. J. Electron. Test. 10 (3) (1997)
Keerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell, Janak H. Patel
Improving a nonenumerative method to estimate path delay fault coverage. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16 (7) (1997)
Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal
Classification and Test Generation for Path-Delay Faults Using Single Struck-at Fault Tests. J. Electron. Test. 11 (1) (1997)
Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal
An Exact Non-Enumerative Fault Simulator for Path-Delay Faults. ITC (1996)
Lakshminarayana Pappu, Michael L. Bushnell, Vishwani D. Agrawal, Mandyam-Komar Srinivas
Statistical path delay fault coverage estimation for synchronous sequential circuits. VLSI Design (1996)
Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal
Parallel concurrent path-delay fault simulation using single-input change patterns. VLSI Design (1996)
Xinghao Chen, Michael L. Bushnell
Sequential circuit test generation using dynamic justification equivalence. J. Electron. Test. 8 (1) (1996)
Vishwani D. Agrawal, Michael L. Bushnell, Qing Lin
Redundancy Identification Using Transitive Closure. Asian Test Symposium (1996)
Rajesh Ramadoss, Michael L. Bushnell
Test generation for mixed-signal devices using signal flow graphs. VLSI Design (1996)
Imtiaz P. Shaik, Michael L. Bushnell
A graph approach to DFT hardware placement for robust delay fault BIST. VLSI Design (1995)
James Sienicki, Michael L. Bushnell, Prathima Agrawal, Vishwani D. Agrawal
An adaptive distributed algorithm for sequential circuit test generation. EURO-DAC (1995)
Keerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell
Fault coverage estimation by test vector sampling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14 (5) (1995)
Keerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell
Statistical methods for delay fault coverage analysis. VLSI Design (1995)
Xinghao Chen, Michael L. Bushnell
Generation of search state equivalence for automatic test pattern generation. VLSI Design (1995)
Imtiaz P. Shaik, Michael L. Bushnell
Circuit design for low overhead delay-fault BIST using constrained quadratic 0-1 programming . VTS (1995)
James Sienicki, Michael L. Bushnell, Prathima Agrawal, Vishwani D. Agrawal
An asynchronous algorithm for sequential circuit test generation on a network of workstations. VLSI Design (1995)
Mandyam-Komar Srinivas, Vishwani D. Agrawal, Michael L. Bushnell
Functional test generation for path delay faults. Asian Test Symposium (1995)
Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal
Classification and Test Generation for Path-Delay Faults Using Single Stuck-Fault Tests. ITC (1995)
Carolina L. C. Cooper, Michael L. Bushnell
Neural models for transistor and mixed-level test generation. VTS (1994)
Keerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell
FACTS: fault coverage estimation by test vector sampling. VTS (1994)
James Sienicki, Michael L. Bushnell, Sandip Parikh
Graphical Methodology Language for CAD Frameworks. VLSI Design (1994)
Srimat T. Chakradhar, Vishwani D. Agrawal, Michael L. Bushnell
Energy minimization and design for testability. J. Electron. Test. 5 (1) (1994)
Xinghao Chen, Michael L. Bushnell
Dynamic State and Objective Learning for Sequential Circuit Automatic Test Generation Using Decomposition Equivalence. FTCS (1994)
Keerthi Heragu, Michael L. Bushnell, Vishwani D. Agrawal
An Efficient Path Delay Fault Coverage Estimator. DAC (1994)
Sandip Parikh, Michael L. Bushnell, James Sienicki, Ganesh Ramakrishnan
Distributed Computing, Automatic Design, and Error Recovery in the ULYSSES II Framework. EDAC-ETC-EUROASIC (1994)
Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell
Design for Testability for Path Delay faults in Sequential Circuits. DAC (1993)
Srimat T. Chakradhar, Michael L. Bushnell
A solvable class of quadratic 0-1 programming. Discret. Appl. Math. 36 (3) (1992)
Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell
Delay Fault Models and Test Generation for Random Logic Sequential Circuits. DAC (1992)
John Giraldi, Michael L. Bushnell
Search State Equivalence for Redundancy Identification and Test Generation. ITC (1991)
Srimat T. Chakradhar, Vishwani D. Agrawal, Michael L. Bushnell
Automatic Test Generation Using Quadratic 0-1 Programming. DAC (1990)
Daniel R. Brasen, Michael L. Bushnell
MHERTZ: A New Optimization Algorithm for Floorplanning and Global Routing. DAC (1990)
Srimat T. Chakradhar, Vishwani D. Agrawal, Michael L. Bushnell
Polynomial time solvable fault detection problems. FTCS (1990)
Srimat T. Chakradhar, Vishwani D. Agrawal, Michael L. Bushnell, Thomas K. Truong
Neural Net and Boolean Satisfiability Models of Logic Circuits. IEEE Des. Test Comput. 7 (5) (1990)
Srimat T. Chakradhar, Michael L. Bushnell, Vishwani D. Agrawal
Toward massively parallel automatic test generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9 (9) (1990)
John Giraldi, Michael L. Bushnell
EST: The New Frontier in Automatic Test-Pattern Generation. DAC (1990)
Michael L. Bushnell, Stephen W. Director
Automated design tool execution in the Ulysses design environment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8 (3) (1989)
Xinghao Chen, Michael L. Bushnell
A Module Area Estimator for VLSI Layout. DAC (1988)
Srimat T. Chakradhar, Michael L. Bushnell, Vishwani D. Agrawal
Automatic test generation using neural networks. ICCAD (1988)
Michael L. Bushnell, Stephen W. Director
ULYSSES - a knowledge-based VLSI design environment. Artif. Intell. Eng. 2 (1) (1987)
Michael L. Bushnell, Pierre Haren
Guest editorial. Artif. Intell. Eng. 1 (2) (1986)
Michael L. Bushnell, Stephen W. Director
VLSI CAD tool integration using the Ulysses environment. DAC (1986)
David P. LaPotin, Sani R. Nassif, Jayanth V. Rajan, Michael L. Bushnell, John A. Nestor
DIF: A framework for VLSI multi-level representation. Integr. 2 (3) (1984)