Design of Variable Input Delay Gates for Low Dynamic Power Circuits.

Tezaswi Raja Vishwani D. Agrawal Michael L. Bushnell

Published in: PATMOS (2005)

Keyphrases

power dissipation
logic circuits
design process
power consumption
chip design
clock gating
case study
design methodology
power reduction
data sets
artificial intelligence
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computer aided
low power
digital circuits
digital signal processing