Tezaswi Raja

Publication Activity (10 Years)

Years Active: 2003-2024
Publications (10 Years): 2

Top Topics

Classification Scheme

Energy Dissipation

Reconfigurable Architecture

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Siddharth Saxena, Sudhir S. Kudva, Vijay Srinivasan, Miguel Rodriguez, Walter Li, Shalimar Rasheed, Gaurav Ajwani, Tezaswi Raja, Santosh A, C. Thomas Gray
A Distributed Power Supply Scheme with Dropout Voltage in Range 6mv-500mv and a Low Overhead Retention Mode. CICC (2024)
Matthew Fojtik, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Stephen G. Tell, Brian Zimmer, Tezaswi Raja, Kevin Zhou, William J. Dally, Brucek Khailany
A Fine-Grained GALS SoC with Pausible Adaptive Clocking in 16 nm FinFET. ASYNC (2019)
Ignatius Bezzam, Chakravarthy Mathiazhagan, Tezaswi Raja, Shoba Krishnan
An Energy-Recovering Reconfigurable Series Resonant Clocking Scheme for Wide Frequency Operation. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2015)
Ignatius Bezzam, Shoba Krishnan, Tezaswi Raja, Chakravarthy Mathiazhagan
Low power low voltage wide frequency resonant clock and data circuits for power reductions. LASCAS (2013)
Tezaswi Raja, Samiha Mourad
Digital Logic Implementation in Memristor-Based Crossbars - A Tutorial. DELTA (2010)
Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell
Variable Input Delay CMOS Logic for Low Power Design. IEEE Trans. Very Large Scale Integr. Syst. 17 (10) (2009)
Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell
Transistor Sizing of Logic Gates to Maximize Input Delay Variability. J. Low Power Electron. 2 (1) (2006)
Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell
Design of Variable Input Delay Gates for Low Dynamic Power Circuits. PATMOS (2005)
Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell
Variable Input Delay CMOS Logic for Low Power Design. VLSI Design (2005)
Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell
A Tuturial on the Emerging Nanotechnology Devices. VLSI Design (2004)
Tezaswi Raja, Manish Parashar
Using a Jini based desktop Grid for test vector compaction and a refined economic model. CCGRID (2004)
Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell
CMOS Circuit Design for Minimum Dynamic Power and Highest Speed. VLSI Design (2004)
Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell
Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program. VLSI Design (2003)