William J. Dally

ORCID

Publication Activity (10 Years)

Years Active: 1985-2024
Publications (10 Years): 76

Top Venues

CoRR

IEEE J. Solid State Circuits

ISCA

ICLR (Poster)

Publications

Walker J. Turner, John W. Poulton, Yoshinori Nishi, Xi Chen, Brian Zimmer, Sanquan Song, John M. Wilson, William J. Dally, C. Thomas Gray
Leveraging Micro-Bump Pitch Scaling to Accelerate Interposer Link Bandwidths for Future High-Performance Compute Applications. CICC (2024)
Yoshinori Nishi, John W. Poulton, Walker J. Turner, Xi Chen, Sanquan Song, Brian Zimmer, Stephen G. Tell, Nikola Nedovic, John M. Wilson, William J. Dally, C. Thomas Gray
A 0.190-pJ/bit 25.2-Gb/s/wire Inverter-Based AC-Coupled Transceiver for Short-Reach Die-to-Die Interfaces in 5-nm CMOS. IEEE J. Solid State Circuits 59 (4) (2024)
Ben Keller, Rangharajan Venkatesan, Steve Dai, Stephen G. Tell, Brian Zimmer, Charbel Sakr, William J. Dally, C. Thomas Gray, Brucek Khailany
A 95.6-TOPS/W Deep Learning Inference Accelerator With Per-Vector Scaled 4-bit Quantization in 5 nm. IEEE J. Solid State Circuits 58 (4) (2023)
Tuofei Chen, Lei Gu, William J. Dally, Juan Rivas-Davila, John D. Fox
A Novel High-Efficiency Three-Phase Multilevel PV Inverter With Reduced DC-Link Capacitance. IEEE Trans. Ind. Electron. 70 (5) (2023)
Song Han, Xingyu Liu, Huizi Mao, Jing Pu, Ardavan Pedram, Mark A. Horowitz, William J. Dally
Retrospective: EIE: Efficient Inference Engine on Sparse and Compressed Neural Network. CoRR (2023)
Yoshinori Nishi, John W. Poulton, Walker J. Turner, Xi Chen, Sanquan Song, Brian Zimmer, Stephen G. Tell, Nikola Nedovic, John M. Wilson, William J. Dally, C. Thomas Gray
A 0.297-pJ/Bit 50.4-Gb/s/Wire Inverter-Based Short-Reach Simultaneous Bi-Directional Transceiver for Die-to-Die Interface in 5-nm CMOS. IEEE J. Solid State Circuits 58 (4) (2023)
Chenzhuo Zhu, Alexander C. Rucker, Yawen Wang, William J. Dally
SatIn: Hardware for Boolean Satisfiability Inference. CoRR (2023)
Yoshinori Nishi, John W. Poulton, Xi Chen, Sanquan Song, Brian Zimmer, Walker J. Turner, Stephen G. Tell, Nikola Nedovic, John M. Wilson, William J. Dally, C. Thomas Gray
A 0.190-pJ/bit 25.2-Gb/s/wire Inverter-Based AC-Coupled Transceiver for Short-Reach Die-to-Die Interfaces in 5-nm CMOS. VLSI Technology and Circuits (2023)
Zaid Qureshi, Vikram Sharma Mailthody, Isaac Gelado, Seungwon Min, Amna Masood, Jeongmin Park, Jinjun Xiong, C. J. Newburn, Dmitri Vainbrand, I-Hsin Chung, Michael Garland, William J. Dally, Wen-Mei W. Hwu
GPU-Initiated On-Demand High-Throughput Storage Access in the BaM System Architecture. ASPLOS (2) (2023)
Zaid Qureshi, Vikram Sharma Mailthody, Isaac Gelado, Seungwon Min, Amna Masood, Jeongmin Park, Jinjun Xiong, C. J. Newburn, Dmitri Vainbrand, I-Hsin Chung, Michael Garland, William J. Dally, Wen-Mei W. Hwu
BaM: A Case for Enabling Fine-grain High Throughput GPU-Orchestrated Access to Storage. CoRR (2022)
Yoshinori Nishi, John W. Poulton, Xi Chen, Sanquan Song, Brian Zimmer, Walker J. Turner, Stephen G. Tell, Nikola Nedovic, John M. Wilson, William J. Dally, C. Thomas Gray
A 0.297-pJ/bit 50.4-Gb/s/wire Inverter-Based Short-Reach Simultaneous Bidirectional Transceiver for Die-to-Die Interface in 5nm CMOS. VLSI Technology and Circuits (2022)
Peter M. Kogge, William J. Dally
Frontier vs the Exascale Report: Why so long? and Are We Really There Yet? PMBS@SC (2022)
Charbel Sakr, Steve Dai, Rangharajan Venkatesan, Brian Zimmer, William J. Dally, Brucek Khailany
Optimal Clipping and Magnitude-aware Differentiation for Improved Quantization-aware Training. ICML (2022)
William J. Dally
On the model of computation: point. Commun. ACM 65 (9) (2022)
Jiawei Zhao, Steve Dai, Rangharajan Venkatesan, Brian Zimmer, Mustafa Fayez Ali, Ming-Yu Liu, Brucek Khailany, William J. Dally, Anima Anandkumar
LNS-Madam: Low-Precision Training in Logarithmic Number System Using Multiplicative Weight Update. IEEE Trans. Computers 71 (12) (2022)
Charbel Sakr, Steve Dai, Rangharajan Venkatesan, Brian Zimmer, William J. Dally, Brucek Khailany
Optimal Clipping and Magnitude-aware Differentiation for Improved Quantization-aware Training. CoRR (2022)
Ben Keller, Rangharajan Venkatesan, Steve Dai, Stephen G. Tell, Brian Zimmer, William J. Dally, C. Thomas Gray, Brucek Khailany
A 17-95.6 TOPS/W Deep Learning Inference Accelerator with Per-Vector Scaled 4-bit Quantization for Transformers in 5nm. VLSI Technology and Circuits (2022)
Steve Dai, Rangharajan Venkatesan, Mark Ren, Brian Zimmer, William J. Dally, Brucek Khailany
VS-Quant: Per-vector Scaled Quantization for Accurate Low-Precision Neural Network Inference. MLSys (2021)
William J. Dally, Stephen W. Keckler, David Blair Kirk
Evolution of the Graphics Processing Unit (GPU). IEEE Micro 41 (6) (2021)
Steve Dai, Rangharajan Venkatesan, Haoxing Ren, Brian Zimmer, William J. Dally, Brucek Khailany
VS-Quant: Per-vector Scaled Quantization for Accurate Low-Precision Neural Network Inference. CoRR (2021)
Huizi Mao, Sibo Zhu, Song Han, William J. Dally
PatchNet - Short-range Template Matching for Efficient Video Processing. CoRR (2021)
Guy E. Blelloch, William J. Dally, Margaret Martonosi, Uzi Vishkin, Katherine A. Yelick
SPAA'21 Panel Paper: Architecture-Friendly Algorithms versus Algorithm-Friendly Architectures. SPAA (2021)
William J. Dally
OP-VENT: A Low-Cost, Easily Assembled, Open-Source Medical Ventilator. GetMobile Mob. Comput. Commun. 25 (4) (2021)
Yakun Sophia Shao, Jason Clemons, Rangharajan Venkatesan, Brian Zimmer, Matthew Fojtik, Nan Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Stephen G. Tell, Yanqing Zhang, William J. Dally, Joel S. Emer, C. Thomas Gray, Brucek Khailany, Stephen W. Keckler
Simba: scaling deep-learning inference with chiplet-based architecture. Commun. ACM 64 (6) (2021)
Zhekai Zhang, Hanrui Wang, Song Han, William J. Dally
SpArch: Efficient Architecture for Sparse Matrix Multiplication. CoRR (2020)
Zhekai Zhang, Hanrui Wang, Song Han, William J. Dally
SpArch: Efficient Architecture for Sparse Matrix Multiplication. HPCA (2020)
Brian Zimmer, Rangharajan Venkatesan, Yakun Sophia Shao, Jason Clemons, Matthew Fojtik, Nan Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Stephen G. Tell, Yanqing Zhang, William J. Dally, Joel S. Emer, C. Thomas Gray, Stephen W. Keckler, Brucek Khailany
A 0.32-128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm. IEEE J. Solid State Circuits 55 (4) (2020)
Brucek Khailany, Haoxing Ren, Steve Dai, Saad Godil, Ben Keller, Robert Kirby, Alicia Klinefelter, Rangharajan Venkatesan, Yanqing Zhang, Bryan Catanzaro, William J. Dally
Accelerating Chip Design With Machine Learning. IEEE Micro 40 (6) (2020)
William J. Dally, Yatish Turakhia, Song Han
Domain-specific hardware accelerators. Commun. ACM 63 (7) (2020)
Jongho Kim, Youngsuk Park, John D. Fox, Stephen P. Boyd, William J. Dally
Optimal Operation of a Plug-in Hybrid Vehicle with Battery Thermal and Degradation Model. ACC (2020)
Milad Mohammadi, Song Han, Ehsan Atoofian, Amirali Baniasadi, Tor M. Aamodt, William J. Dally
Energy Efficient On-Demand Dynamic Branch Prediction Models. IEEE Trans. Computers 69 (3) (2020)
Yatish Turakhia, Gill Bejerano, William J. Dally
Darwin: A Genomics Coprocessor. IEEE Micro 39 (3) (2019)
John W. Poulton, John M. Wilson, Walker J. Turner, Brian Zimmer, Xi Chen, Sudhir S. Kudva, Sanquan Song, Stephen G. Tell, Nikola Nedovic, Wenxu Zhao, Sunil R. Sudhakaran, C. Thomas Gray, William J. Dally
A 1.17-pJ/b, 25-Gb/s/pin Ground-Referenced Single-Ended Serial Link for Off- and On-Package Communication Using a Process- and Temperature-Adaptive Voltage Regulator. IEEE J. Solid State Circuits 54 (1) (2019)
Yatish Turakhia, Gill Bejerano, William J. Dally
Darwin: A Genomics Co-processor Provides up to 15, 000X Acceleration on Long Read Assembly. USENIX Annual Technical Conference (2019)
Rangharajan Venkatesan, Yakun Sophia Shao, Miaorong Wang, Jason Clemons, Steve Dai, Matthew Fojtik, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Yanqing Zhang, Brian Zimmer, William J. Dally, Joel S. Emer, Stephen W. Keckler, Brucek Khailany
MAGNet: A Modular Accelerator Generator for Neural Networks. ICCAD (2019)
Brian Zimmer, Rangharajan Venkatesan, Yakun Sophia Shao, Jason Clemons, Matthew Fojtik, Nan Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Stephen G. Tell, Yanqing Zhang, William J. Dally, Joel S. Emer, C. Thomas Gray, Stephen W. Keckler, Brucek Khailany
A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm. VLSI Circuits (2019)
Huizi Mao, Xiaodong Yang, William J. Dally
A Delay Metric for Video Object Detection: What Average Precision Fails to Tell. CoRR (2019)
Angad S. Rekhi, Brian Zimmer, Nikola Nedovic, Ningxi Liu, Rangharajan Venkatesan, Miaorong Wang, Brucek Khailany, William J. Dally, C. Thomas Gray
Analog/Mixed-Signal Hardware Error Modeling for Deep Learning Inference. DAC (2019)
Yakun Sophia Shao, Jason Clemons, Rangharajan Venkatesan, Brian Zimmer, Matthew Fojtik, Nan Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Stephen G. Tell, Yanqing Zhang, William J. Dally, Joel S. Emer, C. Thomas Gray, Brucek Khailany, Stephen W. Keckler
Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture. MICRO (2019)
Matthew Fojtik, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Stephen G. Tell, Brian Zimmer, Tezaswi Raja, Kevin Zhou, William J. Dally, Brucek Khailany
A Fine-Grained GALS SoC with Pausible Adaptive Clocking in 16 nm FinFET. ASYNC (2019)
Sanquan Song, John Poulton, Xi Chen, Brian Zimmer, Stephen G. Tell, Walker J. Turner, Sudhir S. Kudva, Nikola Nedovic, John M. Wilson, C. Thomas Gray, William J. Dally
A 2-to-20 GHz Multi-Phase Clock Generator with Phase Interpolators Using Injection-Locked Oscillation Buffers for High-Speed IOs in 16nm FinFET. CICC (2019)
Yatish Turakhia, Sneha D. Goenka, Gill Bejerano, William J. Dally
Darwin-WGA: A Co-processor Provides Increased Sensitivity in Whole Genome Alignments with High Speedup. HPCA (2019)
Rangharajan Venkatesan, Yakun Sophia Shao, Brian Zimmer, Jason Clemons, Matthew Fojtik, Nan Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Stephen G. Tell, Yanqing Zhang, William J. Dally, Joel S. Emer, C. Thomas Gray, Stephen W. Keckler, Brucek Khailany
A 0.11 PJ/OP, 0.32-128 Tops, Scalable Multi-Chip-Module-Based Deep Neural Network Accelerator Designed with A High-Productivity vlsi Methodology. Hot Chips Symposium (2019)
Xingyu Liu, Jeff Pool, Song Han, William J. Dally
Efficient Sparse-Winograd Convolutional Neural Networks. ICLR (Poster) (2018)
Huizi Mao, Taeyoung Kong, William J. Dally
CaTDet: Cascaded Tracked Detector for Efficient Object Detection from Video. CoRR (2018)
Walker J. Turner, John W. Poulton, John M. Wilson, Xi Chen, Stephen G. Tell, Matthew Fojtik, Thomas H. Greer, Brian Zimmer, Sanquan Song, Nikola Nedovic, Sudhir S. Kudva, Sunil R. Sudhakaran, Rizwan Bashirullah, Wenxu Zhao, William J. Dally, C. Thomas Gray
Ground-referenced signaling for intra-chip and short-reach chip-to-chip interconnects. CICC (2018)
Song Han, William J. Dally
Bandwidth-efficient deep learning. DAC (2018)
Yatish Turakhia, Gill Bejerano, William J. Dally
Darwin: A Genomics Co-processor Provides up to 15, 000X Acceleration on Long Read Assembly. ASPLOS (2018)
Xingyu Liu, Jeff Pool, Song Han, William J. Dally
Efficient Sparse-Winograd Convolutional Neural Networks. CoRR (2018)
William J. Dally, C. Thomas Gray, John Poulton, Brucek Khailany, John M. Wilson, Larry R. Dennison
Hardware-Enabled Artificial Intelligence. VLSI Circuits (2018)
Jason Platt, Nicholas Moehle, John D. Fox, William J. Dally
Optimal Operation of a Plug-In Hybrid Vehicle. IEEE Trans. Veh. Technol. 67 (11) (2018)
John M. Wilson, Walker J. Turner, John W. Poulton, Brian Zimmer, Xi Chen, Sudhir S. Kudva, Sanquan Song, Stephen G. Tell, Nikola Nedovic, Wenxu Zhao, Sunil R. Sudhakaran, C. Thomas Gray, William J. Dally
A 1.17pJ/b 25Gb/s/pin ground-referenced single-ended serial link for off- and on-package communication in 16nm CMOS using a process- and temperature-adaptive voltage regulator. ISSCC (2018)
Chenzhuo Zhu, Song Han, Huizi Mao, William J. Dally
Trained Ternary Quantization. ICLR (Poster) (2017)
Yatish Turakhia, Subhasis Das, Tor M. Aamodt, William J. Dally
HoLiSwap: Reducing Wire Energy in L1 Caches. CoRR (2017)
Angshuman Parashar, Minsoo Rhu, Anurag Mukkara, Antonio Puglielli, Rangharajan Venkatesan, Brucek Khailany, Joel S. Emer, Stephen W. Keckler, William J. Dally
SCNN: An Accelerator for Compressed-sparse Convolutional Neural Networks. ISCA (2017)
Yujun Lin, Song Han, Huizi Mao, Yu Wang, William J. Dally
Deep Gradient Compression: Reducing the Communication Bandwidth for Distributed Training. CoRR (2017)
Huizi Mao, Song Han, Jeff Pool, Wenshuo Li, Xingyu Liu, Yu Wang, William J. Dally
Exploring the Regularity of Sparse Structure in Convolutional Neural Networks. CoRR (2017)
Milad Mohammadi, Tor M. Aamodt, William J. Dally
CG-OoO: Energy-Efficient Coarse-Grain Out-of-Order Execution Near In-Order Energy with Near Out-of-Order Performance. ACM Trans. Archit. Code Optim. 14 (4) (2017)
Morteza Mardani, Enhao Gong, Joseph Y. Cheng, Shreyas Vasanawala, Greg Zaharchuk, Marcus T. Alley, Neil Thakur, Song Han, William J. Dally, John M. Pauly, Lei Xing
Deep Generative Adversarial Networks for Compressed Sensing Automates MRI. CoRR (2017)
Huizi Mao, Song Han, Jeff Pool, Wenshuo Li, Xingyu Liu, Yu Wang, William J. Dally
Exploring the Granularity of Sparsity in Convolutional Neural Networks. CVPR Workshops (2017)
Xingyu Liu, Song Han, Huizi Mao, William J. Dally
Efficient Sparse-Winograd Convolutional Neural Networks. ICLR (Workshop) (2017)
Angshuman Parashar, Minsoo Rhu, Anurag Mukkara, Antonio Puglielli, Rangharajan Venkatesan, Brucek Khailany, Joel S. Emer, Stephen W. Keckler, William J. Dally
SCNN: An Accelerator for Compressed-sparse Convolutional Neural Networks. CoRR (2017)
Song Han, Jeff Pool, Sharan Narang, Huizi Mao, Enhao Gong, Shijian Tang, Erich Elsen, Peter Vajda, Manohar Paluri, John Tran, Bryan Catanzaro, William J. Dally
DSD: Dense-Sparse-Dense Training for Deep Neural Networks. ICLR (Poster) (2017)
Mike O'Connor, Niladrish Chatterjee, Donghyuk Lee, John M. Wilson, Aditya Agrawal, Stephen W. Keckler, William J. Dally
Fine-grained DRAM: energy-efficient DRAM for extreme bandwidth systems. MICRO (2017)
Niladrish Chatterjee, Mike O'Connor, Donghyuk Lee, Daniel R. Johnson, Stephen W. Keckler, Minsoo Rhu, William J. Dally
Architecting an Energy-Efficient DRAM System for GPUs. HPCA (2017)
Song Han, Xingyu Liu, Huizi Mao, Jing Pu, Ardavan Pedram, Mark A. Horowitz, William J. Dally
EIE: Efficient Inference Engine on Compressed Deep Neural Network. CoRR (2016)
Song Han, Xingyu Liu, Huizi Mao, Jing Pu, Ardavan Pedram, Mark A. Horowitz, William J. Dally
EIE: Efficient Inference Engine on Compressed Deep Neural Network. ISCA (2016)
Song Han, Jeff Pool, Sharan Narang, Huizi Mao, Shijian Tang, Erich Elsen, Bryan Catanzaro, John Tran, William J. Dally
DSD: Regularizing Deep Neural Networks with Dense-Sparse-Dense Training Flow. CoRR (2016)
Forrest N. Iandola, Matthew W. Moskewicz, Khalid Ashraf, Song Han, William J. Dally, Kurt Keutzer
SqueezeNet: AlexNet-level accuracy with 50x fewer parameters and <1MB model size. CoRR (2016)
Subhasis Das, Tor M. Aamodt, William J. Dally
Reuse Distance-Based Probabilistic Cache Replacement. ACM Trans. Archit. Code Optim. 12 (4) (2016)
John M. Wilson, Matthew R. Fojtik, John W. Poulton, Xi Chen, Stephen G. Tell, Thomas H. Greer, C. Thomas Gray, William J. Dally
8.6 A 6.5-to-23.3fJ/b/mm balanced charge-recycling bus in 16nm FinFET CMOS at 1.7-to-2.6Gb/s/wire with clock forwarding and low-crosstalk contraflow wiring. ISSCC (2016)
Song Han, Junlong Kang, Huizi Mao, Yiming Hu, Xin Li, Yubin Li, Dongliang Xie, Hong Luo, Song Yao, Yu Wang, Huazhong Yang, William J. Dally
ESE: Efficient Speech Recognition Engine with Compressed LSTM on FPGA. CoRR (2016)
Mahmut E. Sinangil, John W. Poulton, Matthew R. Fojtik, Thomas H. Greer, Stephen G. Tell, Andreas J. Gotterba, Jesse Wang, Jason Golbus, Brian Zimmer, William J. Dally, C. Thomas Gray
A 28 nm 2 Mbit 6 T SRAM With Highly Configurable Low-Voltage Write-Ability Assist Implementation and Capacitor-Based Sense-Amplifier Input Offset Compensation. IEEE J. Solid State Circuits 51 (2) (2016)
Song Han, Huizi Mao, William J. Dally
Deep Compression: Compressing Deep Neural Network with Pruning, Trained Quantization and Huffman Coding. ICLR (2016)
Milad Mohammadi, Tor M. Aamodt, William J. Dally
CG-OoO: Energy-Efficient Coarse-Grain Out-of-Order Execution. CoRR (2016)
Chenzhuo Zhu, Song Han, Huizi Mao, William J. Dally
Trained Ternary Quantization. CoRR (2016)
Song Han, Jeff Pool, John Tran, William J. Dally
Learning both Weights and Connections for Efficient Neural Network. NIPS (2015)
Subhasis Das, Tor M. Aamodt, William J. Dally
SLIP: reducing wire energy in the memory hierarchy. ISCA (2015)
R. Curtis Harting, William J. Dally
On-Chip Active Messages for Speed, Scalability, and Efficiency. IEEE Trans. Parallel Distributed Syst. 26 (2) (2015)
Nan Jiang, Larry R. Dennison, William J. Dally
Network endpoint congestion control for fine-grained communication. SC (2015)
Song Han, Jeff Pool, John Tran, William J. Dally
Learning both Weights and Connections for Efficient Neural Networks. CoRR (2015)
Milad Mohammadi, Song Han, Tor M. Aamodt, William J. Dally
On-Demand Dynamic Branch Prediction. IEEE Comput. Archit. Lett. 14 (1) (2015)
Oreste Villa, Daniel R. Johnson, Mike O'Connor, Evgeny Bolotin, David W. Nellans, Justin Luitjens, Nikolai Sakharnykh, Peng Wang, Paulius Micikevicius, Anthony Scudiero, Stephen W. Keckler, William J. Dally
Scaling the Power Wall: A Path to Exascale. SC (2014)
William J. Dally, James D. Balfour
Author retrospective for design tradeoffs for tiled CMP on-chip networks. ICS 25th Anniversary (2014)
John W. Poulton, William J. Dally, Xi Chen, John G. Eyles, Thomas H. Greer, Stephen G. Tell, C. Thomas Gray
A 0.54pJ/b 20Gb/s ground-referenced single-ended short-haul serial link in 28nm CMOS for advanced packaging applications. ISSCC (2013)
Nan Jiang, Daniel U. Becker, George Michelogiannakis, James D. Balfour, Brian Towles, David E. Shaw, John Kim, William J. Dally
A detailed and flexible cycle-accurate Network-on-Chip simulator. ISPASS (2013)
William J. Dally, Chris Malachowsky, Stephen W. Keckler
21st century digital design tools. DAC (2013)
John W. Poulton, William J. Dally, Xi Chen, John G. Eyles, Thomas H. Greer, Stephen G. Tell, John M. Wilson, C. Thomas Gray
A 0.54 pJ/b 20 Gb/s Ground-Referenced Single-Ended Short-Reach Serial Link in 28 nm CMOS for Advanced Packaging Applications. IEEE J. Solid State Circuits 48 (12) (2013)
George Michelogiannakis, Nan Jiang, Daniel Becker, William J. Dally
Channel reservation protocol for over-subscribed channels and destinations. SC (2013)
George Michelogiannakis, William J. Dally
Elastic Buffer Flow Control for On-Chip Networks. IEEE Trans. Computers 62 (2) (2013)
Mark Gebhart, Stephen W. Keckler, Brucek Khailany, Ronny Krashinsky, William J. Dally
Unifying Primary Cache, Scratch, and Register File Memories in a Throughput Processor. MICRO (2012)
Nan Jiang, Daniel U. Becker, George Michelogiannakis, William J. Dally
Network congestion avoidance through Speculative Reservation. HPCA (2012)
Mark Gebhart, Daniel R. Johnson, David Tarjan, Stephen W. Keckler, William J. Dally, Erik Lindholm, Kevin Skadron
A Hierarchical Thread Scheduler and Register File for Energy-Efficient Throughput Processors. ACM Trans. Comput. Syst. 30 (2) (2012)
Daniel U. Becker, Nan Jiang, George Michelogiannakis, William J. Dally
Adaptive Backpressure: Efficient buffer management for on-chip networks. ICCD (2012)
R. Curtis Harting, Vishal Parikh, William J. Dally
The utility of fast active messages on many-core chips: Efficient supercomputing project. Hot Chips Symposium (2011)
Mark Gebhart, Stephen W. Keckler, William J. Dally
A compile-time managed multi-level register file hierarchy. MICRO (2011)
Stephen W. Keckler, William J. Dally, Brucek Khailany, Michael Garland, David Glasco
GPUs and the Future of Parallel Computing. IEEE Micro 31 (5) (2011)
Yves Robert, William J. Dally, Jack J. Dongarra, Satoshi Matsuoka, Robert Schreiber, Horst D. Simon, Uzi Vishkin
Panel Statement. IPDPS (2011)
George Michelogiannakis, Nan Jiang, Daniel Becker, William J. Dally
Packet Chaining: Efficient Single-Cycle Allocation for On-Chip Networks. IEEE Comput. Archit. Lett. 10 (2) (2011)
George Michelogiannakis, Nan Jiang, Daniel Becker, William J. Dally
Packet chaining: efficient single-cycle allocation for on-chip networks. MICRO (2011)

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Publication Activity (10 Years)

Top Topics

Top Venues

William J. Dally