Nan Jiang

Publication Activity (10 Years)

Years Active: 2008-2021
Publications (10 Years): 7

Top Topics

Congestion Avoidance

Top Venues

Publications

Yakun Sophia Shao, Jason Clemons, Rangharajan Venkatesan, Brian Zimmer, Matthew Fojtik, Nan Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Stephen G. Tell, Yanqing Zhang, William J. Dally, Joel S. Emer, C. Thomas Gray, Brucek Khailany, Stephen W. Keckler
Simba: scaling deep-learning inference with chiplet-based architecture. Commun. ACM 64 (6) (2021)
Brian Zimmer, Rangharajan Venkatesan, Yakun Sophia Shao, Jason Clemons, Matthew Fojtik, Nan Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Stephen G. Tell, Yanqing Zhang, William J. Dally, Joel S. Emer, C. Thomas Gray, Stephen W. Keckler, Brucek Khailany
A 0.32-128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm. IEEE J. Solid State Circuits 55 (4) (2020)
Brian Zimmer, Rangharajan Venkatesan, Yakun Sophia Shao, Jason Clemons, Matthew Fojtik, Nan Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Stephen G. Tell, Yanqing Zhang, William J. Dally, Joel S. Emer, C. Thomas Gray, Stephen W. Keckler, Brucek Khailany
A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm. VLSI Circuits (2019)
Yakun Sophia Shao, Jason Clemons, Rangharajan Venkatesan, Brian Zimmer, Matthew Fojtik, Nan Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Stephen G. Tell, Yanqing Zhang, William J. Dally, Joel S. Emer, C. Thomas Gray, Brucek Khailany, Stephen W. Keckler
Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture. MICRO (2019)
Rangharajan Venkatesan, Yakun Sophia Shao, Brian Zimmer, Jason Clemons, Matthew Fojtik, Nan Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Stephen G. Tell, Yanqing Zhang, William J. Dally, Joel S. Emer, C. Thomas Gray, Stephen W. Keckler, Brucek Khailany
A 0.11 PJ/OP, 0.32-128 Tops, Scalable Multi-Chip-Module-Based Deep Neural Network Accelerator Designed with A High-Productivity vlsi Methodology. Hot Chips Symposium (2019)
Matthias A. Blumrich, Nan Jiang, Larry R. Dennison
Exploiting idle resources in a high-radix switch for supplemental storage. SC (2018)
Nan Jiang, Larry R. Dennison, William J. Dally
Network endpoint congestion control for fine-grained communication. SC (2015)
Nan Jiang, Daniel U. Becker, George Michelogiannakis, James D. Balfour, Brian Towles, David E. Shaw, John Kim, William J. Dally
A detailed and flexible cycle-accurate Network-on-Chip simulator. ISPASS (2013)
George Michelogiannakis, Nan Jiang, Daniel Becker, William J. Dally
Channel reservation protocol for over-subscribed channels and destinations. SC (2013)
Nan Jiang, Daniel U. Becker, George Michelogiannakis, William J. Dally
Network congestion avoidance through Speculative Reservation. HPCA (2012)
Daniel U. Becker, Nan Jiang, George Michelogiannakis, William J. Dally
Adaptive Backpressure: Efficient buffer management for on-chip networks. ICCD (2012)
George Michelogiannakis, Nan Jiang, Daniel Becker, William J. Dally
Packet Chaining: Efficient Single-Cycle Allocation for On-Chip Networks. IEEE Comput. Archit. Lett. 10 (2) (2011)
George Michelogiannakis, Nan Jiang, Daniel Becker, William J. Dally
Packet chaining: efficient single-cycle allocation for on-chip networks. MICRO (2011)
Nan Jiang, John Kim, William J. Dally
Indirect adaptive routing on large scale interconnection networks. ISCA (2009)
Nathaniel Ross Pinckney, Thomas Barr, Michael Dayringer, Matthew McKnett, Nan Jiang, Carl Nygaard, David Money Harris, Joel Stanley, Braden Phillips
A MIPS R2000 implementation. DAC (2008)