A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm.
Brian ZimmerRangharajan VenkatesanYakun Sophia ShaoJason ClemonsMatthew FojtikNan JiangBen KellerAlicia KlinefelterNathaniel Ross PinckneyPriyanka RainaStephen G. TellYanqing ZhangWilliam J. DallyJoel S. EmerC. Thomas GrayStephen W. KecklerBrucek KhailanyPublished in: VLSI Circuits (2019)
Keyphrases
- neural network
- high speed
- back propagation
- low cost
- artificial neural networks
- neural network model
- neural nets
- pattern recognition
- fuzzy logic
- host computer
- multi layer perceptron
- parallel implementation
- nm technology
- neural network is trained
- analog vlsi
- multi layer
- feed forward
- fault diagnosis
- arc consistency
- high density
- multilayer perceptron
- circuit design
- single chip
- learning vector quantization
- compute intensive
- self organizing maps
- genetic algorithm