John M. Wilson

Publication Activity (10 Years)

Years Active: 1999-2024
Publications (10 Years): 15

Top Topics

Preprocessing Phase

Top Venues

IEEE J. Solid State Circuits

VLSI Technology and Circuits

Publications

Walker J. Turner, John W. Poulton, Yoshinori Nishi, Xi Chen, Brian Zimmer, Sanquan Song, John M. Wilson, William J. Dally, C. Thomas Gray
Leveraging Micro-Bump Pitch Scaling to Accelerate Interposer Link Bandwidths for Future High-Performance Compute Applications. CICC (2024)
Yoshinori Nishi, John W. Poulton, Walker J. Turner, Xi Chen, Sanquan Song, Brian Zimmer, Stephen G. Tell, Nikola Nedovic, John M. Wilson, William J. Dally, C. Thomas Gray
A 0.190-pJ/bit 25.2-Gb/s/wire Inverter-Based AC-Coupled Transceiver for Short-Reach Die-to-Die Interfaces in 5-nm CMOS. IEEE J. Solid State Circuits 59 (4) (2024)
Yoshinori Nishi, John W. Poulton, Walker J. Turner, Xi Chen, Sanquan Song, Brian Zimmer, Stephen G. Tell, Nikola Nedovic, John M. Wilson, William J. Dally, C. Thomas Gray
A 0.297-pJ/Bit 50.4-Gb/s/Wire Inverter-Based Short-Reach Simultaneous Bi-Directional Transceiver for Die-to-Die Interface in 5-nm CMOS. IEEE J. Solid State Circuits 58 (4) (2023)
Yoshinori Nishi, John W. Poulton, Xi Chen, Sanquan Song, Brian Zimmer, Walker J. Turner, Stephen G. Tell, Nikola Nedovic, John M. Wilson, William J. Dally, C. Thomas Gray
A 0.190-pJ/bit 25.2-Gb/s/wire Inverter-Based AC-Coupled Transceiver for Short-Reach Die-to-Die Interfaces in 5-nm CMOS. VLSI Technology and Circuits (2023)
Yoshinori Nishi, John W. Poulton, Xi Chen, Sanquan Song, Brian Zimmer, Walker J. Turner, Stephen G. Tell, Nikola Nedovic, John M. Wilson, William J. Dally, C. Thomas Gray
A 0.297-pJ/bit 50.4-Gb/s/wire Inverter-Based Short-Reach Simultaneous Bidirectional Transceiver for Die-to-Die Interface in 5nm CMOS. VLSI Technology and Circuits (2022)
Xi Chen, Nikola Nedovic, Stephen G. Tell, Sudhir S. Kudva, Brian Zimmer, Thomas H. Greer, John W. Poulton, Sanquan Song, Walker J. Turner, John M. Wilson, C. Thomas Gray
6.6 Reference-Noise Compensation Scheme for Single-Ended Package-to-Package Links. ISSCC (2020)
John W. Poulton, John M. Wilson, Walker J. Turner, Brian Zimmer, Xi Chen, Sudhir S. Kudva, Sanquan Song, Stephen G. Tell, Nikola Nedovic, Wenxu Zhao, Sunil R. Sudhakaran, C. Thomas Gray, William J. Dally
A 1.17-pJ/b, 25-Gb/s/pin Ground-Referenced Single-Ended Serial Link for Off- and On-Package Communication Using a Process- and Temperature-Adaptive Voltage Regulator. IEEE J. Solid State Circuits 54 (1) (2019)
Sanquan Song, John Poulton, Xi Chen, Brian Zimmer, Stephen G. Tell, Walker J. Turner, Sudhir S. Kudva, Nikola Nedovic, John M. Wilson, C. Thomas Gray, William J. Dally
A 2-to-20 GHz Multi-Phase Clock Generator with Phase Interpolators Using Injection-Locked Oscillation Buffers for High-Speed IOs in 16nm FinFET. CICC (2019)
Walker J. Turner, John W. Poulton, John M. Wilson, Xi Chen, Stephen G. Tell, Matthew Fojtik, Thomas H. Greer, Brian Zimmer, Sanquan Song, Nikola Nedovic, Sudhir S. Kudva, Sunil R. Sudhakaran, Rizwan Bashirullah, Wenxu Zhao, William J. Dally, C. Thomas Gray
Ground-referenced signaling for intra-chip and short-reach chip-to-chip interconnects. CICC (2018)
Sudhir S. Kudva, Sanquan Song, John W. Poulton, John M. Wilson, Wenxu Zhao, C. Thomas Gray
A switching linear regulator based on a fast-self-clocked comparator with very low probability of meta-stability and a parallel analog ripple control module. CICC (2018)
William J. Dally, C. Thomas Gray, John Poulton, Brucek Khailany, John M. Wilson, Larry R. Dennison
Hardware-Enabled Artificial Intelligence. VLSI Circuits (2018)
John M. Wilson, Walker J. Turner, John W. Poulton, Brian Zimmer, Xi Chen, Sudhir S. Kudva, Sanquan Song, Stephen G. Tell, Nikola Nedovic, Wenxu Zhao, Sunil R. Sudhakaran, C. Thomas Gray, William J. Dally
A 1.17pJ/b 25Gb/s/pin ground-referenced single-ended serial link for off- and on-package communication in 16nm CMOS using a process- and temperature-adaptive voltage regulator. ISSCC (2018)
Laura Fick, Dennis Sylvester, John W. Poulton, John M. Wilson, C. Thomas Gray
A 25 Gb/s 470 μW active inductor equalizer for ground referenced signaling receivers. ISCAS (2017)
Mike O'Connor, Niladrish Chatterjee, Donghyuk Lee, John M. Wilson, Aditya Agrawal, Stephen W. Keckler, William J. Dally
Fine-grained DRAM: energy-efficient DRAM for extreme bandwidth systems. MICRO (2017)
John M. Wilson, Matthew R. Fojtik, John W. Poulton, Xi Chen, Stephen G. Tell, Thomas H. Greer, C. Thomas Gray, William J. Dally
8.6 A 6.5-to-23.3fJ/b/mm balanced charge-recycling bus in 16nm FinFET CMOS at 1.7-to-2.6Gb/s/wire with clock forwarding and low-crosstalk contraflow wiring. ISSCC (2016)
John W. Poulton, William J. Dally, Xi Chen, John G. Eyles, Thomas H. Greer, Stephen G. Tell, John M. Wilson, C. Thomas Gray
A 0.54 pJ/b 20 Gb/s Ground-Referenced Single-Ended Short-Reach Serial Link in 28 nm CMOS for Advanced Packaging Applications. IEEE J. Solid State Circuits 48 (12) (2013)
John C. Eble, Scott Best, Brian S. Leibowitz, Lei Luo, Robert Palmer, John M. Wilson, Jared Zerbe, Amir Amirkhany, Nhat Nguyen
Power-efficient I/O design considerations for high-bandwidth applications. CICC (2011)
Brian S. Leibowitz, Robert Palmer, John Poulton, Yohan Frans, Simon Li, John M. Wilson, Michael Bucher, Andrew M. Fuller, John G. Eyles, Marko Aleksic, Trey Greer, Nhat Nguyen
A 4.3 GB/s Mobile Memory Interface With Power-Efficient Bandwidth Scaling. IEEE J. Solid State Circuits 45 (4) (2010)
Paul D. Franzon, John M. Wilson, Ming Li
Thermal isolation in 3D chip stacks using vacuum gaps and capacitive or inductive communications. 3DIC (2010)
Liang Zhang, John M. Wilson, Rizwan Bashirullah, Lei Luo, Jian Xu, Paul D. Franzon
A 32-Gb/s On-Chip Bus With Driver Pre-Emphasis Signaling. IEEE Trans. Very Large Scale Integr. Syst. 17 (9) (2009)
Liang Zhang, John M. Wilson, Rizwan Bashirullah, Lei Luo, Jian Xu, Paul D. Franzon
Voltage-Mode Driver Preemphasis Technique For On-Chip Global Buses. IEEE Trans. Very Large Scale Integr. Syst. 15 (2) (2007)
Lei Luo, John M. Wilson, Stephen E. Mick, Jian Xu, Liang Zhang, Evan Erickson, Paul D. Franzon
A 36Gb/s ACCI Multi-Channel Bus using a Fully Differential Pulse Receiver. CICC (2006)
Lei Luo, John M. Wilson, Stephen E. Mick, Jian Xu, Liang Zhang, Paul D. Franzon
3 gb/s AC coupled chip-to-chip communication using a low swing pulse receiver. IEEE J. Solid State Circuits 41 (1) (2006)
Liang Zhang, John M. Wilson, Rizwan Bashirullah, Lei Luo, Jian Xu, Paul D. Franzon
A 32Gb/s On-chip Bus with Driver Pre-emphasis Signaling. CICC (2006)
Liang Zhang, John M. Wilson, Rizwan Bashirullah, Lei Luo, Jian Xu, Paul D. Franzon
Driver pre-emphasis techniques for on-chip global buses. ISLPED (2005)
W. Rhett Davis, John M. Wilson, Stephen E. Mick, Jian Xu, Hao Hua, Christopher Mineo, Ambarish M. Sule, Michael B. Steer, Paul D. Franzon
Demystifying 3D ICs: The Pros and Cons of Going Vertical. IEEE Des. Test Comput. 22 (6) (2005)
Liang Zhang, Wentai Liu, Rizwan Bashirullah, John M. Wilson, Paul D. Franzon
Simplified delay design guidelines for on-chip global interconnects. ACM Great Lakes Symposium on VLSI (2004)
Stephen E. Mick, John M. Wilson, Paul D. Franzon
4 Gbps high-density AC coupled interconnection. CICC (2002)
B. E. Duewer, John M. Wilson, D. A. Winick, Paul D. Franzon
MEMS-Based Capacitor Arrays for Programmable Interconnect and RF Applications. ARVLSI (1999)