Marko Aleksic

Publication Activity (10 Years)

Years Active: 2001-2018
Publications (10 Years): 1

Top Topics

Cmos Technology

Database Workloads

Top Venues

IEEE J. Solid State Circuits

Publications

Marko Aleksic, Vanja Jovanovic
Non-physical Painting Restoration in Improved Reality. VRTCH (2018)
Reza Navid, E.-Hung Chen, Masum Hossain, Brian S. Leibowitz, Jihong Ren, Chuen-Huei Adam Chou, Barry Daly, Marko Aleksic, Bruce Su, Simon Li, Makarand Shirasgaonkar, Fred Heaton, Jared Zerbe, John C. Eble
A 40 Gb/s Serial Link Transceiver in 28 nm CMOS Technology. IEEE J. Solid State Circuits 50 (4) (2015)
Marko Aleksic
A 3.2-GHz 1.3-mW ILO phase rotator for burst-mode mobile memory I/O in 28-nm low-leakage CMOS. ESSCIRC (2014)
E.-Hung Chen, Masum Hossain, Brian S. Leibowitz, Reza Navid, Jihong Ren, Chuen-Huei Adam Chou, Barry Daly, Marko Aleksic, Bruce Su, Simon Li, Makarand Shirasgaonkar, Fred Heaton, Jared Zerbe, John C. Eble
A 40-Gb/s serial link transceiver in 28-nm CMOS technology. VLSIC (2014)
Brian S. Leibowitz, Robert Palmer, John Poulton, Yohan Frans, Simon Li, John M. Wilson, Michael Bucher, Andrew M. Fuller, John G. Eyles, Marko Aleksic, Trey Greer, Nhat Nguyen
A 4.3 GB/s Mobile Memory Interface With Power-Efficient Bandwidth Scaling. IEEE J. Solid State Circuits 45 (4) (2010)
Marko Aleksic, Peyman Razaghi, Wei Yu
Capacity of a Class of Modulo-Sum Relay Channels. IEEE Trans. Inf. Theory 55 (3) (2009)
Haechang Lee, Kun-Yung Ken Chang, Jung-Hoon Chun, Ting Wu, Yohan Frans, Brian S. Leibowitz, Nhat Nguyen, T. J. Chin, Kambiz Kaviani, Jie Shen, Xudong Shi, Wendemagegnehu T. Beyene, Simon Li, Reza Navid, Marko Aleksic, Fred S. Lee, Fredy Quan, Jared Zerbe, Rich Perego, Fariborz Assaderaghi
A 16 Gb/s/Link, 64 GB/s Bidirectional Asymmetric Memory Interface. IEEE J. Solid State Circuits 44 (4) (2009)
Marko Aleksic, Nikola Nedovic, K. Wayne Current, Vojin G. Oklobdzija
Jitter Analysis of Nonautonomous MOS Current-Mode Logic Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. (10) (2008)
Marko Aleksic, Peyman Razaghi, Wei Yu
Capacity of a Class of Modulo-Sum Relay Channels. ISIT (2007)
Marko Aleksic, Peyman Razaghi, Wei Yu
Capacity of a Class of Modulo-Sum Relay Channels CoRR (2007)
Rastislav Lukac, Konstantinos N. Plataniotis, Dimitrios Hatzinakos, Marko Aleksic
A new CFA interpolation framework. Signal Process. 86 (7) (2006)
Wei Yu, Marko Aleksic
Coding for the blackwell channel: a survey propagation approach. ISIT (2005)
Marko Aleksic, Nikola Nedovic, K. Wayne Current, Vojin G. Oklobdzija
A New Model for Timing Jitter Caused by Device Noise in Current-Mode Logic Frequency Dividers. PATMOS (2005)
Rastislav Lukac, Konstantinos N. Plataniotis, Dimitrios Hatzinakos, Marko Aleksic
A novel cost effective demosaicing approach. IEEE Trans. Consumer Electron. 50 (1) (2004)
Nikola Nedovic, Marko Aleksic, Vojin G. Oklobdzija
Comparative analysis of double-edge versus single-edge triggered clocked storage elements. ISCAS (5) (2002)
Nikola Nedovic, Marko Aleksic, Vojin G. Oklobdzija
Conditional pre-charge techniques for power-efficient dual-edge clocking. ISLPED (2002)
Nikola Nedovic, Marko Aleksic, Vojin G. Oklobdzija
Timing Characterization of Dual-edge Triggered Flip-flops. ICCD (2001)
Nikola Nedovic, Marko Aleksic, Vojin G. Oklobdzija
Conditional techniques for low power consumption flip-flops. ICECS (2001)