Makarand Shirasgaonkar

Publication Activity (10 Years)

Years Active: 2012-2015
Publications (10 Years): 0

Top Topics

Cmos Technology

Power Dissipation

Generalization Bounds

Top Venues

IEEE J. Solid State Circuits

Publications

Reza Navid, E.-Hung Chen, Masum Hossain, Brian S. Leibowitz, Jihong Ren, Chuen-Huei Adam Chou, Barry Daly, Marko Aleksic, Bruce Su, Simon Li, Makarand Shirasgaonkar, Fred Heaton, Jared Zerbe, John C. Eble
A 40 Gb/s Serial Link Transceiver in 28 nm CMOS Technology. IEEE J. Solid State Circuits 50 (4) (2015)
Makarand Shirasgaonkar, Roxanne Vu, Deborah Dressler, Nhat Nguyen, Kambiz Kaviani, Yueyong Wang
An Adaptive Body-Biased Clock Generation System in 28nm CMOS. VLSI Design (2014)
E.-Hung Chen, Masum Hossain, Brian S. Leibowitz, Reza Navid, Jihong Ren, Chuen-Huei Adam Chou, Barry Daly, Marko Aleksic, Bruce Su, Simon Li, Makarand Shirasgaonkar, Fred Heaton, Jared Zerbe, John C. Eble
A 40-Gb/s serial link transceiver in 28-nm CMOS technology. VLSIC (2014)
Masum Hossain, E.-Hung Chen, Reza Navid, Brian S. Leibowitz, Chuen-Huei Adam Chou, Simon Li, Myeong-Jae Park, Jihong Ren, Barry Daly, Bruce Su, Makarand Shirasgaonkar, Fred Heaton, Jared Zerbe, John C. Eble
A 4×40 Gb/s quad-lane CDR with shared frequency tracking and data dependent jitter filtering. VLSIC (2014)
Masum Hossain, Kambiz Kaviani, Barry Daly, Makarand Shirasgaonkar, Wayne D. Dettloff, Teva Stone, Kashinath Prabhu, Brian Tsang, John C. Eble, Jared Zerbe
A 6.4/3.2/1.6 Gb/s low power interface with all digital clock multiplier for on-the-fly rate switching. CICC (2012)